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authorRizwan Qureshi <rizwan.qureshi@intel.com>2015-11-19 16:30:18 +0530
committerPatrick Georgi <pgeorgi@google.com>2016-01-19 16:22:06 +0100
commitfefce185335232aade9e512a1cbe94da27578768 (patch)
tree1511ee6bc0664936211373ebbdd4ec6cf6d522c4 /src/mainboard
parent497ff3ce7ce91d0d58ea60f58ad70422cb0ff2b8 (diff)
downloadcoreboot-fefce185335232aade9e512a1cbe94da27578768.tar.xz
intel/kunimitsu: Enable FspSkipMpInit token
MP init is already handled in coreboot, but it is also part of FSP FSP has a implemented a provision to allow FSP to skip MP init and let coreboot handle it. BRANCH=none BUG=chrome-os-partner:44805 TEST=Build and booted in kunimitsu with SkipMpInit enabled from CB. CQ-DEPEND=CL:310192 Change-Id: Idd9b1424f23765ce227005a322ac72d9e9fc841a Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 5c52d0f0cc5d480c87fababc3316009e3ade6e45 Original-Change-Id: I9d92046d0237680b8d562814a9a605a36efb9516 Original-Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com> Original-Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/312926 Original-Commit-Ready: Preetham Chandrian <preetham.chandrian@intel.com> Original-Tested-by: Preetham Chandrian <preetham.chandrian@intel.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/12992 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/mainboard')
-rw-r--r--src/mainboard/intel/kunimitsu/devicetree.cb2
1 files changed, 2 insertions, 0 deletions
diff --git a/src/mainboard/intel/kunimitsu/devicetree.cb b/src/mainboard/intel/kunimitsu/devicetree.cb
index e75959e075..75bb7c40f8 100644
--- a/src/mainboard/intel/kunimitsu/devicetree.cb
+++ b/src/mainboard/intel/kunimitsu/devicetree.cb
@@ -126,6 +126,8 @@ chip soc/intel/skylake
.voltage_limit = 0x5F0 \
}"
+ register "FspSkipMpInit" = "1"
+
# Enable Root port 1 and 5.
register "PcieRpEnable[0]" = "1"
register "PcieRpEnable[4]" = "1"