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authorTristan Corrick <tristan@corrick.kiwi>2018-12-30 00:59:04 +1300
committerPatrick Georgi <pgeorgi@google.com>2019-01-03 18:10:27 +0000
commit09a5323480fae9ad20075751cad9d1f25d61a3ab (patch)
treebe02372a60027e167f4cd88d90bbeb23bba029e6 /src/mainboard
parentfff243461cf2a7676243ae4f51494736cdadfdf3 (diff)
downloadcoreboot-09a5323480fae9ad20075751cad9d1f25d61a3ab.tar.xz
mb/asrock/h81m-hds: Move GPIO header to a linked C file
Using a linked C file is the standard approach for GPIO settings. Change-Id: I6a5ca65bc1553bd382589d67379eafd03dc0b0a3 Signed-off-by: Tristan Corrick <tristan@corrick.kiwi> Reviewed-on: https://review.coreboot.org/c/30503 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Diffstat (limited to 'src/mainboard')
-rw-r--r--src/mainboard/asrock/h81m-hds/Makefile.inc1
-rw-r--r--src/mainboard/asrock/h81m-hds/gpio.c (renamed from src/mainboard/asrock/h81m-hds/gpio.h)5
-rw-r--r--src/mainboard/asrock/h81m-hds/romstage.c2
3 files changed, 2 insertions, 6 deletions
diff --git a/src/mainboard/asrock/h81m-hds/Makefile.inc b/src/mainboard/asrock/h81m-hds/Makefile.inc
index 94bd1cfe7c..7c1bf9ecd4 100644
--- a/src/mainboard/asrock/h81m-hds/Makefile.inc
+++ b/src/mainboard/asrock/h81m-hds/Makefile.inc
@@ -14,4 +14,5 @@
## GNU General Public License for more details.
##
+romstage-y += gpio.c
ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
diff --git a/src/mainboard/asrock/h81m-hds/gpio.h b/src/mainboard/asrock/h81m-hds/gpio.c
index dde3e531cf..a03a52e726 100644
--- a/src/mainboard/asrock/h81m-hds/gpio.h
+++ b/src/mainboard/asrock/h81m-hds/gpio.c
@@ -14,9 +14,6 @@
* GNU General Public License for more details.
*/
-#ifndef ASROCK_H81M_HDS_GPIO_H
-#define ASROCK_H81M_HDS_GPIO_H
-
#include <southbridge/intel/common/gpio.h>
static const struct pch_gpio_set1 pch_gpio_set1_mode = {
@@ -164,5 +161,3 @@ const struct pch_gpio_map mainboard_gpio_map = {
.reset = &pch_gpio_set3_reset,
},
};
-
-#endif /* ASROCK_H81M_HDS_GPIO_H */
diff --git a/src/mainboard/asrock/h81m-hds/romstage.c b/src/mainboard/asrock/h81m-hds/romstage.c
index f3c2b3bfdb..c6bef9f0b4 100644
--- a/src/mainboard/asrock/h81m-hds/romstage.c
+++ b/src/mainboard/asrock/h81m-hds/romstage.c
@@ -20,10 +20,10 @@
#include <cpu/intel/haswell/haswell.h>
#include <northbridge/intel/haswell/haswell.h>
#include <northbridge/intel/haswell/pei_data.h>
+#include <southbridge/intel/common/gpio.h>
#include <southbridge/intel/lynxpoint/pch.h>
#include <superio/nuvoton/common/nuvoton.h>
#include <superio/nuvoton/nct6776/nct6776.h>
-#include "gpio.h"
static const struct rcba_config_instruction rcba_config[] = {
RCBA_SET_REG_16(D31IR, DIR_ROUTE(PIRQA, PIRQD, PIRQC, PIRQA)),