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| author | Matt DeVillier <matt.devillier@puri.sm> | 2020-11-05 11:34:50 -0600 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-11-09 07:47:53 +0000 |
| commit | 0e4f37f7a7c7812bf15b83fd841f22b497c41e9c (patch) | |
| tree | 0aaa6925c32f0c8e41a18e6245e6045f3767fee1 /src/mainboard | |
| parent | e9523926152490d3f1c70ff8773b87ee54084e55 (diff) | |
| download | coreboot-0e4f37f7a7c7812bf15b83fd841f22b497c41e9c.tar.xz | |
mb/purism/librem_mini: Update smbios_slot_desc for M.2/WLAN
Add strings for M.2 keying and number of PCIe lanes.
Change-Id: I2e13749b50263ee5c2388a419bc8d784af6bd880
Signed-off-by: Matt DeVillier <matt.devillier@puri.sm>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47251
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard')
| -rw-r--r-- | src/mainboard/purism/librem_cnl/variants/librem_mini/devicetree.cb | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/mainboard/purism/librem_cnl/variants/librem_mini/devicetree.cb b/src/mainboard/purism/librem_cnl/variants/librem_mini/devicetree.cb index becb9468c7..e2135b7fa9 100644 --- a/src/mainboard/purism/librem_cnl/variants/librem_mini/devicetree.cb +++ b/src/mainboard/purism/librem_cnl/variants/librem_mini/devicetree.cb @@ -197,7 +197,7 @@ chip soc/intel/cannonlake register "PcieRpLtrEnable[7]" = "1" # ClkSrcUsage must be set to free-run since SRCCLKREQ2 is NC register "PcieClkSrcUsage[2]" = "0x80" - smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthOther" + smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthOther" "M.2/E 2230" "SlotDataBusWidth1X" end device pci 1d.0 off end # PCI Express Port 9 device pci 1d.1 on # PCI Express Port 10 |