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authorMartin Roth <martinroth@chromium.org>2019-05-11 12:51:44 -0600
committerPatrick Georgi <pgeorgi@google.com>2019-05-13 09:26:45 +0000
commit2f0bbbfe9f3b3d68d75eabd35280fe8aaa9d8619 (patch)
treecc0a9dbd1088ba17748dd6f1b1e920d96629d44b /src/mainboard
parentef9e85bbfdb24d228f1e6c37d916025c5d06ea53 (diff)
downloadcoreboot-2f0bbbfe9f3b3d68d75eabd35280fe8aaa9d8619.tar.xz
mb/lenovo/s230u: Rewrite trigger inversion ACPI code
The GPIO invert registers are already defined in the PCH code, so just use the 8-bit versions of the registers instead of creating a new GPIO field for the single bits. This allows us to get rid of the Field(GPIO...) code that's causing problems with IASL version 20190509. Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: Iac5dfb71b3a2b5a25c05a403cf5f403c7acecaaf Reviewed-on: https://review.coreboot.org/c/coreboot/+/32753 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Diffstat (limited to 'src/mainboard')
-rw-r--r--src/mainboard/lenovo/s230u/acpi/gpe.asl23
1 files changed, 12 insertions, 11 deletions
diff --git a/src/mainboard/lenovo/s230u/acpi/gpe.asl b/src/mainboard/lenovo/s230u/acpi/gpe.asl
index a69f5629b1..e6f4153aca 100644
--- a/src/mainboard/lenovo/s230u/acpi/gpe.asl
+++ b/src/mainboard/lenovo/s230u/acpi/gpe.asl
@@ -16,15 +16,6 @@
Scope (_GPE)
{
- Field(GPIO, ByteAcc, NoLock, Preserve)
- {
- Offset(0x2c), // GPIO Invert
- , 2,
- GV02, 1,
- , 1,
- GV04, 1,
- }
-
Name (PDET, Zero)
Method (PNOT, 2, Serialized) {
ShiftLeft (Arg0, Arg1, Local0)
@@ -39,10 +30,20 @@ Scope (_GPE)
}
}
+ Method (TINV, 2, Serialized) {
+ ShiftLeft (One, Arg1, Local0)
+ If (LEqual (Arg0, Zero)) {
+ Not (Local0, Local0)
+ And (GIV0, Local0, GIV0)
+ } Else {
+ Or (GIV0, Local0, GIV0)
+ }
+ }
+
/* Palm detect sensor 1 */
Method (_L12, 0, NotSerialized) {
// Invert trigger
- Store(GP02, GV02)
+ TINV (GP02, 2)
PNOT (GP02, 0)
}
@@ -50,7 +51,7 @@ Scope (_GPE)
/* Palm detect sensor 2 */
Method (_L14, 0, NotSerialized) {
// Invert trigger
- Store(GP04, GV04)
+ TINV (GP04, 4)
PNOT (GP04, 1)
}