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| author | Rudolf Marek <r.marek@assembler.cz> | 2013-11-12 16:46:47 +0100 |
|---|---|---|
| committer | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2013-11-19 23:21:16 +0100 |
| commit | 38c78889c5dfeda842e3dd8b8698549cd5e71021 (patch) | |
| tree | fdb5a741b0279f5e9a026b38efebfef7dc559877 /src/mainboard | |
| parent | 113a3668489507f5b14ccea4daae0216021bf228 (diff) | |
| download | coreboot-38c78889c5dfeda842e3dd8b8698549cd5e71021.tar.xz | |
Asus F2A85-M: Fix S3 memory power cut-off
The power to memory is lost during the the suspend, activate
the 3VSBSW# which switches the power during S3 suspend sequence.
As a result resuming from suspend to RAM works now, but now the
GPP ports of the Hudson southbridge are gone after resume from S3.
The devices 15.0 and 15.1 are disabled (decode as ffff) and
therefore anything behind them too [1].
[1] http://www.coreboot.org/pipermail/coreboot/2013-November/076620.html
fam15tn hudson PCIe GPP ports off after resume
Change-Id: Id953313ee4400a03a2ad8ca09e39a5e0d5f92524
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Reviewed-on: http://review.coreboot.org/4041
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Diffstat (limited to 'src/mainboard')
| -rw-r--r-- | src/mainboard/asus/f2a85-m/romstage.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/mainboard/asus/f2a85-m/romstage.c b/src/mainboard/asus/f2a85-m/romstage.c index 5d01bb44fe..031bb50d5f 100644 --- a/src/mainboard/asus/f2a85-m/romstage.c +++ b/src/mainboard/asus/f2a85-m/romstage.c @@ -90,6 +90,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) sbxxx_enable_48mhzout(); it8712f_kill_watchdog(); it8712f_enable_serial(0, CONFIG_TTYS0_BASE); + it8712f_enable_3vsbsw(); console_init(); /* turn on secondary smbus at b20 */ |