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| author | Aaron Durbin <adurbin@chromium.org> | 2016-07-21 10:20:58 -0500 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2016-07-22 18:51:29 +0200 |
| commit | 48f662d941b124e48f0accdf3947d2957e7bbfed (patch) | |
| tree | 6915cc39ad096363f530368aaa7201f6488e851d /src/mainboard | |
| parent | dd8ed42ed6bf94259aa6bc81138e894e43ef4008 (diff) | |
| download | coreboot-48f662d941b124e48f0accdf3947d2957e7bbfed.tar.xz | |
soc/intel/apollolake: clarify meaning of LPDDR4 density meaning
The 'dram density' is a misnomer because the memory initialization
code treats that input parameter as a per rank density. Therefore,
update the variables to further clarify how it's actually being
used.
BUG=chrome-os-partner:55446
Change-Id: Ie4c944f35b531812205ac0bb1c70f39ac401495e
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/15773
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Diffstat (limited to 'src/mainboard')
| -rw-r--r-- | src/mainboard/google/reef/romstage.c | 20 |
1 files changed, 10 insertions, 10 deletions
diff --git a/src/mainboard/google/reef/romstage.c b/src/mainboard/google/reef/romstage.c index 74ead51bea..f9743b5f34 100644 --- a/src/mainboard/google/reef/romstage.c +++ b/src/mainboard/google/reef/romstage.c @@ -78,16 +78,16 @@ static const struct lpddr4_sku skus[] = { */ [0] = { .speed = LP4_SPEED_2400, - .ch0_density = LP4_8Gb_DENSITY, - .ch1_density = LP4_8Gb_DENSITY, + .ch0_rank_density = LP4_8Gb_DENSITY, + .ch1_rank_density = LP4_8Gb_DENSITY, .ch0_dual_rank = 1, .ch1_dual_rank = 1, }, /* K4F8E304HB-MGCJ - both logical channels */ [1] = { .speed = LP4_SPEED_2400, - .ch0_density = LP4_8Gb_DENSITY, - .ch1_density = LP4_8Gb_DENSITY, + .ch0_rank_density = LP4_8Gb_DENSITY, + .ch1_rank_density = LP4_8Gb_DENSITY, }, /* * MT53B512M32D2NP-062WT:C - both logical channels. While the parts @@ -96,22 +96,22 @@ static const struct lpddr4_sku skus[] = { */ [2] = { .speed = LP4_SPEED_2400, - .ch0_density = LP4_8Gb_DENSITY, - .ch1_density = LP4_8Gb_DENSITY, + .ch0_rank_density = LP4_8Gb_DENSITY, + .ch1_rank_density = LP4_8Gb_DENSITY, .ch0_dual_rank = 1, .ch1_dual_rank = 1, }, /* MT53B256M32D1NP-062 WT:C - both logical channels */ [3] = { .speed = LP4_SPEED_2400, - .ch0_density = LP4_8Gb_DENSITY, - .ch1_density = LP4_8Gb_DENSITY, + .ch0_rank_density = LP4_8Gb_DENSITY, + .ch1_rank_density = LP4_8Gb_DENSITY, }, /* K4F8E304HB-MGCH - both logical channels */ [PROTO_SKU] = { .speed = LP4_SPEED_2400, - .ch0_density = LP4_8Gb_DENSITY, - .ch1_density = LP4_8Gb_DENSITY, + .ch0_rank_density = LP4_8Gb_DENSITY, + .ch1_rank_density = LP4_8Gb_DENSITY, }, }; |