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authorBill XIE <persmule@hardenedlinux.org>2019-12-23 13:53:56 +0800
committerPatrick Georgi <pgeorgi@google.com>2019-12-26 10:39:42 +0000
commit5dd4bf3644e13ad65edf2244ea672850a40e95e4 (patch)
tree733dd21e37d49722408c85e25423d690f921dc9c /src/mainboard
parente69798b5ae43d0a71fcbe6e2b38b0dc8edf404bf (diff)
downloadcoreboot-5dd4bf3644e13ad65edf2244ea672850a40e95e4.tar.xz
mb/gigabyte/ga-b75m-d3h: enable superspeed ports for all variants
Unlike other Panther Point boards, the ga-b75m-d3h lacks definitions to wire SuperSpeed-capable ports to XHCI in its devicetree, causing these ports being wired to the second EHCI, and only working as USB 2.0 ports. The missing register definitions are added to fix that. Tested on my ga-b75-d3v board. Change-Id: Ida4de26f1a493ead83065b1ab27c0c684a074513 Signed-off-by: Bill XIE <persmule@hardenedlinux.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37912 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/mainboard')
-rw-r--r--src/mainboard/gigabyte/ga-b75m-d3h/devicetree.cb3
1 files changed, 3 insertions, 0 deletions
diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/devicetree.cb b/src/mainboard/gigabyte/ga-b75m-d3h/devicetree.cb
index 57b4960a12..7b470677b0 100644
--- a/src/mainboard/gigabyte/ga-b75m-d3h/devicetree.cb
+++ b/src/mainboard/gigabyte/ga-b75m-d3h/devicetree.cb
@@ -38,6 +38,9 @@ chip northbridge/intel/sandybridge
register "sata_port_map" = "0x3f"
register "sata_interface_speed_support" = "0x3"
+ register "xhci_switchable_ports" = "0xf"
+ register "superspeed_capable_ports" = "0xf"
+
register "pcie_port_coalesce" = "0"
register "docking_supported" = "0"
register "c2_latency" = "0x0065"