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authorPiotr Król <piotr.krol@3mdeb.com>2018-05-04 17:40:11 +0200
committerPatrick Georgi <pgeorgi@google.com>2018-09-15 11:36:01 +0000
commit694d18a6418bea102850e1695ad4d71fe831a113 (patch)
treebcb2442796597ea3c8afbde93978feaca7155cc5 /src/mainboard
parent9ef07d8623d308b2bc764a35aa6380f3d16e6f90 (diff)
downloadcoreboot-694d18a6418bea102850e1695ad4d71fe831a113.tar.xz
pcengines/apu2: enable IOMMU for all apu2 variants
IOMMU was tested on Xen 4.8 and Linux kernel 4.14.33. Following feature set is enabled: (XEN) AMD-Vi: Disabled HAP memory map sharing with IOMMU (XEN) AMD-Vi: IOMMU Extended Features: (XEN) - Peripheral Page Service Request (XEN) - Guest Translation (XEN) - Invalidate All Command (XEN) - Guest APIC supported (XEN) - Performance Counters (XEN) AMD-Vi: IOMMU 0 Enabled. Change-Id: I6dbfae78849248f3532caa78974c8f2ce61a530d Signed-off-by: Piotr Król <piotr.krol@3mdeb.com> Reviewed-on: https://review.coreboot.org/26116 Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Reviewed-by: Alexander Couzens <lynxis@fe80.eu> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard')
-rw-r--r--src/mainboard/pcengines/apu2/variants/apu2/devicetree.cb2
-rw-r--r--src/mainboard/pcengines/apu2/variants/apu3/devicetree.cb2
-rw-r--r--src/mainboard/pcengines/apu2/variants/apu4/devicetree.cb2
-rw-r--r--src/mainboard/pcengines/apu2/variants/apu5/devicetree.cb2
4 files changed, 4 insertions, 4 deletions
diff --git a/src/mainboard/pcengines/apu2/variants/apu2/devicetree.cb b/src/mainboard/pcengines/apu2/variants/apu2/devicetree.cb
index 4f3206408e..2905e2cf1f 100644
--- a/src/mainboard/pcengines/apu2/variants/apu2/devicetree.cb
+++ b/src/mainboard/pcengines/apu2/variants/apu2/devicetree.cb
@@ -25,7 +25,7 @@ chip northbridge/amd/pi/00730F01/root_complex
chip northbridge/amd/pi/00730F01 # PCI side of HT root complex
device pci 0.0 on end # Root Complex
- device pci 0.2 off end # IOMMU
+ device pci 0.2 on end # IOMMU
device pci 1.0 off end # Internal Graphics P2P bridge 0x9804
device pci 1.1 off end # Internal Multimedia
device pci 2.0 on end # PCIe Host Bridge
diff --git a/src/mainboard/pcengines/apu2/variants/apu3/devicetree.cb b/src/mainboard/pcengines/apu2/variants/apu3/devicetree.cb
index c4312914e2..4da123e78f 100644
--- a/src/mainboard/pcengines/apu2/variants/apu3/devicetree.cb
+++ b/src/mainboard/pcengines/apu2/variants/apu3/devicetree.cb
@@ -25,7 +25,7 @@ chip northbridge/amd/pi/00730F01/root_complex
chip northbridge/amd/pi/00730F01 # PCI side of HT root complex
device pci 0.0 on end # Root Complex
- device pci 0.2 off end # IOMMU
+ device pci 0.2 on end # IOMMU
device pci 1.0 off end # Internal Graphics P2P bridge 0x9804
device pci 1.1 off end # Internal Multimedia
device pci 2.0 on end # PCIe Host Bridge
diff --git a/src/mainboard/pcengines/apu2/variants/apu4/devicetree.cb b/src/mainboard/pcengines/apu2/variants/apu4/devicetree.cb
index 9859255fad..b95afab7cb 100644
--- a/src/mainboard/pcengines/apu2/variants/apu4/devicetree.cb
+++ b/src/mainboard/pcengines/apu2/variants/apu4/devicetree.cb
@@ -25,7 +25,7 @@ chip northbridge/amd/pi/00730F01/root_complex
chip northbridge/amd/pi/00730F01 # PCI side of HT root complex
device pci 0.0 on end # Root Complex
- device pci 0.2 off end # IOMMU
+ device pci 0.2 on end # IOMMU
device pci 1.0 off end # Internal Graphics P2P bridge 0x9804
device pci 1.1 off end # Internal Multimedia
device pci 2.0 on end # PCIe Host Bridge
diff --git a/src/mainboard/pcengines/apu2/variants/apu5/devicetree.cb b/src/mainboard/pcengines/apu2/variants/apu5/devicetree.cb
index 4bdaaaf834..b5700f8141 100644
--- a/src/mainboard/pcengines/apu2/variants/apu5/devicetree.cb
+++ b/src/mainboard/pcengines/apu2/variants/apu5/devicetree.cb
@@ -25,7 +25,7 @@ chip northbridge/amd/pi/00730F01/root_complex
chip northbridge/amd/pi/00730F01 # PCI side of HT root complex
device pci 0.0 on end # Root Complex
- device pci 0.2 off end # IOMMU
+ device pci 0.2 on end # IOMMU
device pci 1.0 off end # Internal Graphics P2P bridge 0x9804
device pci 1.1 off end # Internal Multimedia
device pci 2.0 on end # PCIe Host Bridge