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authorMaulik V Vaghela <maulik.v.vaghela@intel.com>2020-04-21 20:21:34 +0530
committerPatrick Georgi <pgeorgi@google.com>2020-05-05 13:01:09 +0000
commit733ef79424f0260aeaf949386db11121f18d92fb (patch)
tree58c0031b64ac1e41e56ea6ef66076899f543ddd7 /src/mainboard
parentd4ad3f537f2fc478d5904c34d1f06234c30de1c9 (diff)
downloadcoreboot-733ef79424f0260aeaf949386db11121f18d92fb.tar.xz
mb/intel/jasperlake_rvp: Configure IP specific GPIOs
This patch configures all IP related GPIOs as per mainboard schematics. Till now, we were relying on FSP to do IP specific GPIO programming but now we'll program all GPIOs from mainboard. This will remove ambiguity of GPIO programming done by FSP and coreboot will do full GPIO programming Programming GPIOs of following IPs - I2C - Emmc - Display - CPU specific gpio (SLP lines) - Cnvi - SD BUG=None BRANCH=None TEST=compile coreboot and checked that all IP functionality working. Change-Id: I98583b768cbd8ab4af536b31d758cb1cee93edfb Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40572 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-by: V Sowmya <v.sowmya@intel.com> Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
Diffstat (limited to 'src/mainboard')
-rw-r--r--src/mainboard/intel/jasperlake_rvp/variants/jslrvp/gpio.c192
1 files changed, 173 insertions, 19 deletions
diff --git a/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/gpio.c b/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/gpio.c
index 9b86839119..39c14704af 100644
--- a/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/gpio.c
+++ b/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/gpio.c
@@ -7,18 +7,35 @@
/* Pad configuration in ramstage*/
static const struct pad_config gpio_table[] = {
- /* ToDo: Fill other gpio configuration */
/* WWAN_WAKE_N */
PAD_CFG_GPI_SCI(GPP_A10, NONE, DEEP, LEVEL, INVERT),
+ /* DDI1_HPD */
+ PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1),
+
+ /* DDI0_HPD */
+ PAD_CFG_NF(GPP_A17, NONE, DEEP, NF1),
+
/* M.2_WWAN_DISABLE_N */
PAD_CFG_GPO(GPP_A19, 1, PLTRST),
+ /* PMC_CORE_VID0 */
+ PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1),
+
+ /* PMC_CORE_VID1 */
+ PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1),
+
+ /* PMC_SLP_S0_N */
+ PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1),
+
+ /* PMC_PLT_RST_N */
+ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),
+
/* M.2_WLAN_PERST_N */
PAD_CFG_GPO(GPP_B17, 1, PLTRST),
- /* GSPI1_CS# */
+ /* GSPI1_CS0_N */
PAD_CFG_NF(GPP_B19, NONE, DEEP, NF1),
/* GSPI1_CLK */
@@ -30,7 +47,7 @@ static const struct pad_config gpio_table[] = {
/* GSPI1_MOSI */
PAD_CFG_NF(GPP_B22, NONE, DEEP, NF1),
- /*PCH_INT_ODL*/
+ /* DDI2_HPD */
PAD_CFG_NF(GPP_B23, NONE, DEEP, NF1),
/* WWAN_PERST_N */
@@ -39,7 +56,7 @@ static const struct pad_config gpio_table[] = {
/* M2_WWAN_SSD_SKT2_CFG2 */
PAD_CFG_GPI(GPP_C3, NONE, PLTRST),
- /*SLP_LAN_N*/
+ /* SLP_LAN_N */
PAD_CFG_GPO(GPP_C7, 0, PLTRST),
/* I2C0_SDA */
@@ -54,31 +71,145 @@ static const struct pad_config gpio_table[] = {
/* BT_RF_KILL_N */
PAD_CFG_GPO(GPP_D1, 1, PLTRST),
- /*LAN_RST_N*/
+ /* LAN_RST_N */
PAD_CFG_GPO(GPP_D6, 1, PLTRST),
- /* I2S_MCLK */
+ /* AVS_I2S_MCLK */
PAD_CFG_NF(GPP_D18, NONE, DEEP, NF1),
+ /* CNV_MFUART2_RXD */
+ PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1),
+
+ /* CNV_MFUART2_TXD */
+ PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1),
+
+ /* CNV_PA_BLANKING */
+ PAD_CFG_NF(GPP_D21, NONE, DEEP, NF1),
+
/* WWAN_FCP_OFF_N */
PAD_CFG_GPO(GPP_E3, 1, PLTRST),
- /*FPS_INT*/
+ /* DDI0_DDC_SCL */
+ PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1),
+
+ /* DDI0_DDC_SDA */
+ PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1),
+
+ /* DDI1_DDC_SCL */
+ PAD_CFG_NF(GPP_E15, NONE, DEEP, NF1),
+
+ /* DDI1_DDC_SDA */
+ PAD_CFG_NF(GPP_E16, NONE, DEEP, NF1),
+
+ /* DDI2_DDC_SCL */
+ PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1),
+
+ /* DDI2_DDC_SDA */
+ PAD_CFG_NF(GPP_E18, NONE, DEEP, NF1),
+
+ /* CNV_BRI_DT */
+ PAD_CFG_NF(GPP_E20, NONE, DEEP, NF1),
+
+ /* CNV_BRI_RSP */
+ PAD_CFG_NF(GPP_E21, NONE, DEEP, NF1),
+
+ /* CNV_RGI_DT */
+ PAD_CFG_NF(GPP_E22, NONE, DEEP, NF1),
+
+ /* CNV_RGI_RSP */
+ PAD_CFG_NF(GPP_E23, NONE, DEEP, NF1),
+
+ /* CNV_RF_RESET_B */
+ PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1),
+
+ /* EMMC_CMD */
+ PAD_CFG_NF(GPP_F7, NONE, DEEP, NF1),
+
+ /* EMMC_DATA0 */
+ PAD_CFG_NF(GPP_F8, NONE, DEEP, NF1),
+
+ /* EMMC_DATA1 */
+ PAD_CFG_NF(GPP_F9, NONE, DEEP, NF1),
+
+ /* EMMC_DATA2 */
+ PAD_CFG_NF(GPP_F10, NONE, DEEP, NF1),
+
+ /* EMMC_DATA3 */
+ PAD_CFG_NF(GPP_F11, NONE, DEEP, NF1),
+
+ /* EMMC_DATA4 */
+ PAD_CFG_NF(GPP_F12, NONE, DEEP, NF1),
+
+ /* EMMC_DATA5 */
+ PAD_CFG_NF(GPP_F13, NONE, DEEP, NF1),
+
+ /* EMMC_DATA6 */
+ PAD_CFG_NF(GPP_F14, NONE, DEEP, NF1),
+
+ /* EMMC_DATA7 */
+ PAD_CFG_NF(GPP_F15, NONE, DEEP, NF1),
+
+ /* EMMC_RCLK */
+ PAD_CFG_NF(GPP_F16, NONE, DEEP, NF1),
+
+ /* EMMC_CLK */
+ PAD_CFG_NF(GPP_F17, NONE, DEEP, NF1),
+
+ /* EMMC_RESET_N */
+ PAD_CFG_NF(GPP_F18, NONE, DEEP, NF1),
+
+ /* SD_SDIO_CMD */
+ PAD_CFG_NF(GPP_G0, NONE, DEEP, NF1),
+
+ /* SD_SDIO_D0 */
+ PAD_CFG_NF(GPP_G1, NONE, DEEP, NF1),
+
+ /* SD_SDIO_D1 */
+ PAD_CFG_NF(GPP_G2, NONE, DEEP, NF1),
+
+ /* SD_SDIO_D2 */
+ PAD_CFG_NF(GPP_G3, NONE, DEEP, NF1),
+
+ /* SD_SDIO_D3 */
+ PAD_CFG_NF(GPP_G4, NONE, DEEP, NF1),
+
+ /* SD_SDIO_CD_N */
+ PAD_CFG_NF(GPP_G5, UP_20K, PWROK, NF1),
+
+ /* SD_SDIO_CLK */
+ PAD_CFG_NF(GPP_G6, NONE, DEEP, NF1),
+
+ /* SD_SDIO_WP */
+ PAD_CFG_NF(GPP_G7, DN_20K, PWROK, NF1),
+
+ /* FPS_INT */
PAD_CFG_GPI_APIC(GPP_H0, NONE, PLTRST, LEVEL, INVERT),
+ /* SD_SDIO_PWR_EN_N */
+ PAD_CFG_NF(GPP_H1, NONE, DEEP, NF1),
+
+ /* MODEM_CLKREQ0 */
+ PAD_CFG_NF(GPP_H2, NONE, DEEP, NF3),
+
/* WWAN EN GPIO */
PAD_CFG_GPO(GPP_H7, 1, PLTRST),
+ /* CPU_C10_GATE_N */
+ PAD_CFG_NF(GPP_H10, NONE, DEEP, NF1),
+
/* M.2_BT_I2S2_SCLK */
PAD_CFG_GPI(GPP_H11, NONE, PLTRST),
- /*PCH_INT_ODL*/
+ /* CNV_RF_RESET_N */
+ PAD_CFG_NF(GPP_H12, NONE, DEEP, NF2),
+
+ /* PCH_INT_ODL */
PAD_CFG_GPI_APIC(GPP_H13, NONE, DEEP, EDGE_SINGLE, INVERT),
/* M.2_BT_I2S2_RXD */
PAD_CFG_GPI(GPP_H14, NONE, PLTRST),
- /* I2S1_SCLK */
+ /* AVS_I2S1_SCLK */
PAD_CFG_NF(GPP_H15, NONE, DEEP, NF1),
/* Audio Jack Detection */
@@ -87,26 +218,26 @@ static const struct pad_config gpio_table[] = {
/* M2_CNVI_EN_N */
PAD_CFG_GPO(GPP_H19, 0, PLTRST),
- /* I2S0_SCLK */
+ /* AVS_I2S0_SCLK */
PAD_CFG_NF(GPP_R0, NONE, DEEP, NF2),
- /* I2S0_SFRM */
+ /* AVS_I2S0_SFRM */
PAD_CFG_NF(GPP_R1, NONE, DEEP, NF2),
- /* I2S0_TXD */
+ /* AVS_I2S0_TXD */
PAD_CFG_NF(GPP_R2, NONE, DEEP, NF2),
- /* I2S0_RXD */
+ /* AVS_I2S0_RXD */
PAD_CFG_NF(GPP_R3, NONE, DEEP, NF2),
- /* I2S1_RXD */
+ /* AVS_I2S1_RXD */
PAD_CFG_NF(GPP_R5, NONE, DEEP, NF2),
- /* I2S1_SFRM */
- PAD_CFG_NF(GPP_R6, NONE, DEEP, NF2),
+ /* AVS_I2S1_SFRM */
+ PAD_CFG_NF(GPP_R6, NONE, DEEP, NF1),
- /* I2S1_TXD */
- PAD_CFG_NF(GPP_R7, NONE, DEEP, NF2),
+ /* AVS_I2S1_TXD */
+ PAD_CFG_NF(GPP_R7, NONE, DEEP, NF1),
/* WWAN RST_N */
PAD_CFG_GPO(GPP_S0, 1, DEEP),
@@ -123,6 +254,29 @@ static const struct pad_config gpio_table[] = {
/* DMIC_DATA_0 */
PAD_CFG_NF(GPP_S7, UP_20K, DEEP, NF2),
+ /* PMC_BATLOW_N */
+ PAD_CFG_NF(GPD0, NONE, DEEP, NF1),
+
+ /* PMC_ACPRESENT */
+ PAD_CFG_NF(GPD1, NONE, DEEP, NF1),
+
+ /* LAN_WAKE_N */
+ PAD_CFG_NF(GPD2, NONE, DEEP, NF1),
+
+ /* PMC_PWR_BTN_N */
+ PAD_CFG_NF(GPD3, UP_20K, DEEP, NF1),
+
+ /* PMC_SLP_S3_N */
+ PAD_CFG_NF(GPD4, NONE, DEEP, NF1),
+
+ /* PMC_SLP_S4_N */
+ PAD_CFG_NF(GPD5, NONE, DEEP, NF1),
+
+ /* PMC_SUSCLK */
+ PAD_CFG_NF(GPD8, NONE, DEEP, NF1),
+
+ /* virtual GPIO for SD card detect */
+ PAD_CFG_GPI_GPIO_DRIVER(VGPIO_39, NONE, DEEP),
};
/* Early pad configuration in bootblock */
@@ -140,7 +294,7 @@ static const struct pad_config early_gpio_table[] = {
/* GSPI1_MOSI */
PAD_CFG_NF(GPP_B22, NONE, DEEP, NF1),
- /*PCH_INT_ODL*/
+ /* PCH_INT_ODL */
PAD_CFG_GPI_APIC(GPP_H13, NONE, DEEP, EDGE_SINGLE, INVERT),
};