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authorWisley Chen <wisley.chen@quantatw.com>2016-12-23 04:43:18 -0500
committerAaron Durbin <adurbin@chromium.org>2017-01-03 16:54:09 +0100
commit83560cf004ac25d3386599b9b446eb0794989a83 (patch)
tree00835f30b84dfcff66f0690300d5448873f345ea /src/mainboard
parent0984d1da43dae419695041d9792fa96da91b42aa (diff)
downloadcoreboot-83560cf004ac25d3386599b9b446eb0794989a83.tar.xz
google/snappy: Update DPTF settings
1. Update DPTF TSR1/TSR2 passive/critial trigger points. TSR1 passive point:53, critial point:80 TSR2 passive point:90, critial point:100 2. Update PL1 Min to 4W and PL1 Max to 12W 3. Update thermal relationship table (TRT) setting. BUG=none BRANCH=master TEST=build, boot on snappy dut and verified by thermal team member. Change-Id: I8b4fb178daa7c2e4091a14779a125bd5e943d023 Signed-off-by: Wisley Chen <wisley.chen@quantatw.com> Reviewed-on: https://review.coreboot.org/17955 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/mainboard')
-rw-r--r--src/mainboard/google/reef/variants/snappy/include/variant/acpi/dptf.asl16
1 files changed, 8 insertions, 8 deletions
diff --git a/src/mainboard/google/reef/variants/snappy/include/variant/acpi/dptf.asl b/src/mainboard/google/reef/variants/snappy/include/variant/acpi/dptf.asl
index f0e605be5b..a233c9213a 100644
--- a/src/mainboard/google/reef/variants/snappy/include/variant/acpi/dptf.asl
+++ b/src/mainboard/google/reef/variants/snappy/include/variant/acpi/dptf.asl
@@ -29,12 +29,12 @@
#define DPTF_TSR1_SENSOR_ID 1
#define DPTF_TSR1_SENSOR_NAME "Ambient"
-#define DPTF_TSR1_PASSIVE 48
-#define DPTF_TSR1_CRITICAL 65
+#define DPTF_TSR1_PASSIVE 53
+#define DPTF_TSR1_CRITICAL 80
#define DPTF_TSR2_SENSOR_ID 2
#define DPTF_TSR2_SENSOR_NAME "Charger"
-#define DPTF_TSR2_PASSIVE 85
+#define DPTF_TSR2_PASSIVE 90
#define DPTF_TSR2_CRITICAL 100
#define DPTF_ENABLE_CHARGER
@@ -61,10 +61,10 @@ Name (DTRT, Package () {
#endif
/* CPU Effect on Temp Sensor 1 */
- Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR1, 100, 300, 0, 0, 0, 0 },
+ Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR1, 200, 80, 0, 0, 0, 0 },
/* CPU Effect on Temp Sensor 2 */
- Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR2, 100, 600, 0, 0, 0, 0 },
+ Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR2, 100, 150, 0, 0, 0, 0 },
})
Name (MPPC, Package ()
@@ -72,11 +72,11 @@ Name (MPPC, Package ()
0x2, /* Revision */
Package () { /* Power Limit 1 */
0, /* PowerLimitIndex, 0 for Power Limit 1 */
- 3000, /* PowerLimitMinimum */
- 6000, /* PowerLimitMaximum */
+ 4000, /* PowerLimitMinimum */
+ 12000, /* PowerLimitMaximum */
1000, /* TimeWindowMinimum */
1000, /* TimeWindowMaximum */
- 300 /* StepSize */
+ 200 /* StepSize */
},
Package () { /* Power Limit 2 */
1, /* PowerLimitIndex, 1 for Power Limit 2 */