diff options
author | Stefan Reinauer <reinauer@chromium.org> | 2012-11-16 13:34:48 -0800 |
---|---|---|
committer | Patrick Georgi <patrick@georgi-clan.de> | 2012-11-20 21:56:05 +0100 |
commit | 8ada1526df06cb50a82305e840a5181a3c65575f (patch) | |
tree | f1033ee31bdff4add530dedc74b7c537cd175714 /src/mainboard | |
parent | 82ecf4c582fdab341d88bd80ae3e9a629619c263 (diff) | |
download | coreboot-8ada1526df06cb50a82305e840a5181a3c65575f.tar.xz |
Unify use of bool config variables
e.g.
-#if CONFIG_LOGICAL_CPUS == 1
+#if CONFIG_LOGICAL_CPUS
This will make it easier to switch over to use the config_enabled()
macro later on.
Change-Id: I0bcf223669318a7b1105534087c7675a74c1dd8a
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/1874
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Diffstat (limited to 'src/mainboard')
-rw-r--r-- | src/mainboard/amd/parmer/agesawrapper.c | 2 | ||||
-rw-r--r-- | src/mainboard/amd/parmer/get_bus_conf.c | 4 | ||||
-rw-r--r-- | src/mainboard/amd/parmer/mainboard.c | 2 | ||||
-rw-r--r-- | src/mainboard/amd/parmer/romstage.c | 2 | ||||
-rw-r--r-- | src/mainboard/amd/thatcher/agesawrapper.c | 2 | ||||
-rw-r--r-- | src/mainboard/amd/thatcher/get_bus_conf.c | 4 | ||||
-rw-r--r-- | src/mainboard/amd/thatcher/mainboard.c | 2 | ||||
-rw-r--r-- | src/mainboard/amd/thatcher/romstage.c | 2 | ||||
-rw-r--r-- | src/mainboard/asus/m4a785-m/romstage.c | 2 | ||||
-rw-r--r-- | src/mainboard/siemens/sitemp_g1p1/acpi_tables.c | 4 | ||||
-rw-r--r-- | src/mainboard/tyan/s8226/buildOpts.c | 6 | ||||
-rw-r--r-- | src/mainboard/tyan/s8226/rd890_cfg.h | 4 |
12 files changed, 16 insertions, 20 deletions
diff --git a/src/mainboard/amd/parmer/agesawrapper.c b/src/mainboard/amd/parmer/agesawrapper.c index b82c1c137f..c180800143 100644 --- a/src/mainboard/amd/parmer/agesawrapper.c +++ b/src/mainboard/amd/parmer/agesawrapper.c @@ -479,7 +479,7 @@ agesawrapper_amdlaterunaptask ( return (UINT32)Status; } -#if CONFIG_HAVE_ACPI_RESUME == 1 +#if CONFIG_HAVE_ACPI_RESUME UINT32 agesawrapper_amdinitresume(VOID) { diff --git a/src/mainboard/amd/parmer/get_bus_conf.c b/src/mainboard/amd/parmer/get_bus_conf.c index ad5e1d7696..2636b9e49a 100644 --- a/src/mainboard/amd/parmer/get_bus_conf.c +++ b/src/mainboard/amd/parmer/get_bus_conf.c @@ -47,7 +47,7 @@ u32 sbdn_sb800; static u32 get_bus_conf_done = 0; -#if CONFIG_HAVE_ACPI_RESUME == 1 +#if CONFIG_HAVE_ACPI_RESUME extern u8 acpi_slp_type; #endif void get_bus_conf(void) @@ -78,7 +78,7 @@ void get_bus_conf(void) * of each of the write functions called prior to the ACPI write functions, so this * becomes the best place for this call. */ -#if CONFIG_HAVE_ACPI_RESUME == 1 +#if CONFIG_HAVE_ACPI_RESUME if (acpi_slp_type != 3) { status = agesawrapper_amdinitlate(); if(status) { diff --git a/src/mainboard/amd/parmer/mainboard.c b/src/mainboard/amd/parmer/mainboard.c index 40ad8c5d91..a83cd427f0 100644 --- a/src/mainboard/amd/parmer/mainboard.c +++ b/src/mainboard/amd/parmer/mainboard.c @@ -39,7 +39,7 @@ static void parmer_enable(device_t dev) * The mainboard is the first place that we get control in ramstage. Check * for S3 resume and call the approriate AGESA/CIMx resume functions. */ -#if CONFIG_HAVE_ACPI_RESUME == 1 +#if CONFIG_HAVE_ACPI_RESUME acpi_slp_type = acpi_get_sleep_type(); if (acpi_slp_type == 3) agesawrapper_fchs3earlyrestore(); diff --git a/src/mainboard/amd/parmer/romstage.c b/src/mainboard/amd/parmer/romstage.c index 56fcb574ff..335e56d566 100644 --- a/src/mainboard/amd/parmer/romstage.c +++ b/src/mainboard/amd/parmer/romstage.c @@ -44,7 +44,7 @@ void disable_cache_as_ram(void); void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { u32 val; -#if CONFIG_HAVE_ACPI_RESUME == 1 +#if CONFIG_HAVE_ACPI_RESUME void *resume_backup_memory; #endif val = agesawrapper_amdinitmmio(); diff --git a/src/mainboard/amd/thatcher/agesawrapper.c b/src/mainboard/amd/thatcher/agesawrapper.c index 509f472974..67ac8e9e53 100644 --- a/src/mainboard/amd/thatcher/agesawrapper.c +++ b/src/mainboard/amd/thatcher/agesawrapper.c @@ -479,7 +479,7 @@ agesawrapper_amdlaterunaptask ( return (UINT32)Status; } -#if CONFIG_HAVE_ACPI_RESUME == 1 +#if CONFIG_HAVE_ACPI_RESUME UINT32 agesawrapper_amdinitresume(VOID) { diff --git a/src/mainboard/amd/thatcher/get_bus_conf.c b/src/mainboard/amd/thatcher/get_bus_conf.c index ad5e1d7696..2636b9e49a 100644 --- a/src/mainboard/amd/thatcher/get_bus_conf.c +++ b/src/mainboard/amd/thatcher/get_bus_conf.c @@ -47,7 +47,7 @@ u32 sbdn_sb800; static u32 get_bus_conf_done = 0; -#if CONFIG_HAVE_ACPI_RESUME == 1 +#if CONFIG_HAVE_ACPI_RESUME extern u8 acpi_slp_type; #endif void get_bus_conf(void) @@ -78,7 +78,7 @@ void get_bus_conf(void) * of each of the write functions called prior to the ACPI write functions, so this * becomes the best place for this call. */ -#if CONFIG_HAVE_ACPI_RESUME == 1 +#if CONFIG_HAVE_ACPI_RESUME if (acpi_slp_type != 3) { status = agesawrapper_amdinitlate(); if(status) { diff --git a/src/mainboard/amd/thatcher/mainboard.c b/src/mainboard/amd/thatcher/mainboard.c index 8d4eae2ef1..bc1d591f02 100644 --- a/src/mainboard/amd/thatcher/mainboard.c +++ b/src/mainboard/amd/thatcher/mainboard.c @@ -55,7 +55,7 @@ static void thatcher_enable(device_t dev) * The mainboard is the first place that we get control in ramstage. Check * for S3 resume and call the approriate AGESA/CIMx resume functions. */ -#if CONFIG_HAVE_ACPI_RESUME == 1 +#if CONFIG_HAVE_ACPI_RESUME acpi_slp_type = acpi_get_sleep_type(); if (acpi_slp_type == 3) agesawrapper_fchs3earlyrestore(); diff --git a/src/mainboard/amd/thatcher/romstage.c b/src/mainboard/amd/thatcher/romstage.c index e0cfd02d15..445fe45e72 100644 --- a/src/mainboard/amd/thatcher/romstage.c +++ b/src/mainboard/amd/thatcher/romstage.c @@ -49,7 +49,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) u32 val; u8 byte; device_t dev; -#if CONFIG_HAVE_ACPI_RESUME == 1 +#if CONFIG_HAVE_ACPI_RESUME void *resume_backup_memory; #endif val = agesawrapper_amdinitmmio(); diff --git a/src/mainboard/asus/m4a785-m/romstage.c b/src/mainboard/asus/m4a785-m/romstage.c index f0be2f7793..1fe7b49512 100644 --- a/src/mainboard/asus/m4a785-m/romstage.c +++ b/src/mainboard/asus/m4a785-m/romstage.c @@ -246,7 +246,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) */ BOOL AMD_CB_ManualBUIDSwapList (u8 node, u8 link, const u8 **List) { -#ifndef CONFIG_BOARD_ASUS_M4A785TM +#if !CONFIG_BOARD_ASUS_M4A785TM static const u8 swaplist[] = { 0xFF, CONFIG_HT_CHAIN_UNITID_BASE, CONFIG_HT_CHAIN_END_UNITID_BASE, 0xFF }; /* If the BUID was adjusted in early_ht we need to do the manual override */ if ((CONFIG_HT_CHAIN_UNITID_BASE != 0) && (CONFIG_HT_CHAIN_END_UNITID_BASE != 0)) { diff --git a/src/mainboard/siemens/sitemp_g1p1/acpi_tables.c b/src/mainboard/siemens/sitemp_g1p1/acpi_tables.c index ea69034802..cf17e76442 100644 --- a/src/mainboard/siemens/sitemp_g1p1/acpi_tables.c +++ b/src/mainboard/siemens/sitemp_g1p1/acpi_tables.c @@ -36,10 +36,6 @@ #define DUMP_ACPI_TABLES 0 -#ifndef CONFIG_LINT01_CONVERSION -#define CONFIG_LINT01_CONVERSION 1 -#endif - extern u16 pm_base; /* diff --git a/src/mainboard/tyan/s8226/buildOpts.c b/src/mainboard/tyan/s8226/buildOpts.c index 0f618ecaa1..63c587acb6 100644 --- a/src/mainboard/tyan/s8226/buildOpts.c +++ b/src/mainboard/tyan/s8226/buildOpts.c @@ -202,7 +202,7 @@ CONST MANUAL_BUID_SWAP_LIST ROMDATA s8226_manual_swaplist[2] = } }; -#if CONFIG_HT3_SUPPORT == 1 +#if CONFIG_HT3_SUPPORT /** * The socket and link match values are platform specific * @@ -439,10 +439,10 @@ CONST AP_MTRR_SETTINGS ROMDATA s8226_ap_mtrr_list[] = #define AGESA_ENTRY_INIT_GENERAL_SERVICES TRUE /* -#if (CONFIG_CPU_AMD_AGESA_FAMILY15 == 1) +#if CONFIG_CPU_AMD_AGESA_FAMILY15 #define BLDOPT_REMOVE_FAMILY_10_SUPPORT TRUE #endif -#if (CONFIG_CPU_AMD_AGESA_FAMILY10 == 1) +#if CONFIG_CPU_AMD_AGESA_FAMILY10 #define BLDOPT_REMOVE_FAMILY_15_SUPPORT TRUE #endif */ diff --git a/src/mainboard/tyan/s8226/rd890_cfg.h b/src/mainboard/tyan/s8226/rd890_cfg.h index 8f45019783..3ba25d5006 100644 --- a/src/mainboard/tyan/s8226/rd890_cfg.h +++ b/src/mainboard/tyan/s8226/rd890_cfg.h @@ -31,10 +31,10 @@ * [12..15] - Sublink (1..2), If NB connected to full link than Sublink should be set to 0. */ #ifndef DEFAULT_HT_PATH -#if CONFIG_CPU_AMD_AGESA_FAMILY10 == 1 +#if CONFIG_CPU_AMD_AGESA_FAMILY10 #define DEFAULT_HT_PATH {0x0, 0x3} #endif -#if CONFIG_CPU_AMD_AGESA_FAMILY15 == 1 +#if CONFIG_CPU_AMD_AGESA_FAMILY15 #define DEFAULT_HT_PATH {0x0, 0x1} #endif #endif |