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authorMeera Ravindranath <meera.ravindranath@intel.com>2020-04-27 22:53:40 +0530
committerPatrick Georgi <pgeorgi@google.com>2020-05-01 06:17:39 +0000
commita15eaec1e6975d78687aaea06996464b5a67f14c (patch)
tree34c2130b5311aa86ef20bce7f7ae2e9d33d6a4ff /src/mainboard
parent798fd4b69fb8102d66ac58b6f6bec7f8cd5ea9de (diff)
downloadcoreboot-a15eaec1e6975d78687aaea06996464b5a67f14c.tar.xz
mb/intel/jasperlake_rvp: Select PcieRpClkReqDetect in device tree
This CL selects the PcieRpClkReqDetect for the required root ports which is needed to allow proper clksrc gpio configuration. Also, sets the unused PcieClkSrcUsage to 0xFF. BUG=None BRANCH=None TEST=Build and boot jslrvp with NVMe Change-Id: Ie4ae1365a7621b8be3b795798c171e3f7ea9e487 Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40758 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: V Sowmya <v.sowmya@intel.com> Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Diffstat (limited to 'src/mainboard')
-rw-r--r--src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb9
1 files changed, 9 insertions, 0 deletions
diff --git a/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb b/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb
index cb3d1f3598..1b5e256de7 100644
--- a/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb
+++ b/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb
@@ -67,8 +67,17 @@ chip soc/intel/jasperlake
register "PcieRpEnable[1]" = "1"
register "PcieRpEnable[4]" = "1"
+ # Enable ClkReqDetect 1 for WLAN
+ # Enable ClkReqDetect 4 for NVMe
+ register "PcieRpClkReqDetect[1]" = "1"
+ register "PcieRpClkReqDetect[4]" = "1"
+
register "PcieClkSrcUsage[0]" = "0x04"
register "PcieClkSrcUsage[1]" = "0x01"
+ register "PcieClkSrcUsage[2]" = "0xFF"
+ register "PcieClkSrcUsage[3]" = "0xFF"
+ register "PcieClkSrcUsage[4]" = "0xFF"
+ register "PcieClkSrcUsage[5]" = "0xFF"
register "PcieClkSrcClkReq[0]" = "0x00"
register "PcieClkSrcClkReq[1]" = "0x01"