diff options
author | Patrick Georgi <patrick.georgi@coresystems.de> | 2010-10-05 17:59:12 +0000 |
---|---|---|
committer | Myles Watson <mylesgw@gmail.com> | 2010-10-05 17:59:12 +0000 |
commit | abc0c7791e18dbd97949a49016f9ebedb823ed84 (patch) | |
tree | a8c014275fe0c920ccf47f929ec7fe6a151834ea /src/mainboard | |
parent | 5692c5733633bfb8b23f1111de152eff0233b713 (diff) | |
download | coreboot-abc0c7791e18dbd97949a49016f9ebedb823ed84.tar.xz |
attached patch moves a couple more config flags out of romstage:
CK804_USE_NIC, CK804_USE_ACI, CK804_NUM.
MCP55_USE_NIC, MCP55_USE_ACI, MCP55_NUM.
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Pter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5912 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard')
27 files changed, 24 insertions, 55 deletions
diff --git a/src/mainboard/asus/a8n_e/romstage.c b/src/mainboard/asus/a8n_e/romstage.c index 0f2a5c888a..c0821f9bc6 100644 --- a/src/mainboard/asus/a8n_e/romstage.c +++ b/src/mainboard/asus/a8n_e/romstage.c @@ -42,10 +42,6 @@ #include "cpu/x86/lapic/boot_cpu.c" #include "northbridge/amd/amdk8/reset_test.c" #include "superio/ite/it8712f/it8712f_early_serial.c" - -/* Used by ck894_early_setup(). */ -#define CK804_NUM 1 - #include <cpu/amd/model_fxx_rev.h> #include <console/console.h> #include "northbridge/amd/amdk8/incoherent_ht.c" diff --git a/src/mainboard/gigabyte/m57sli/Kconfig b/src/mainboard/gigabyte/m57sli/Kconfig index 5d84fc0c23..9dbc4486be 100644 --- a/src/mainboard/gigabyte/m57sli/Kconfig +++ b/src/mainboard/gigabyte/m57sli/Kconfig @@ -8,6 +8,8 @@ config BOARD_SPECIFIC_OPTIONS # dummy select NORTHBRIDGE_AMD_AMDK8 select NORTHBRIDGE_AMD_AMDK8_ROOT_COMPLEX select SOUTHBRIDGE_NVIDIA_MCP55 + select MCP55_USE_NIC + select MCP55_USE_AZA select SUPERIO_ITE_IT8716F select SUPERIO_ITE_IT8716F_OVERRIDE_FANCTL select HAVE_BUS_CONFIG diff --git a/src/mainboard/gigabyte/m57sli/romstage.c b/src/mainboard/gigabyte/m57sli/romstage.c index 01c989ab25..47e936808d 100644 --- a/src/mainboard/gigabyte/m57sli/romstage.c +++ b/src/mainboard/gigabyte/m57sli/romstage.c @@ -90,10 +90,6 @@ static inline int spd_read_byte(unsigned device, unsigned address) return smbus_read_byte(device, address); } -#define MCP55_NUM 1 -#define MCP55_USE_NIC 1 -#define MCP55_USE_AZA 1 - #define MCP55_PCI_E_X_0 0 #define MCP55_MB_SETUP \ diff --git a/src/mainboard/msi/ms7135/Kconfig b/src/mainboard/msi/ms7135/Kconfig index 1d3e7d18b1..1f8628d2b0 100644 --- a/src/mainboard/msi/ms7135/Kconfig +++ b/src/mainboard/msi/ms7135/Kconfig @@ -15,6 +15,8 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_MP_TABLE select CACHE_AS_RAM select BOARD_ROMSIZE_KB_512 + select CK804_USE_NIC + select CK804_USE_ACI config MAINBOARD_DIR string diff --git a/src/mainboard/msi/ms7135/romstage.c b/src/mainboard/msi/ms7135/romstage.c index 25c42014b4..78ac703b65 100644 --- a/src/mainboard/msi/ms7135/romstage.c +++ b/src/mainboard/msi/ms7135/romstage.c @@ -43,10 +43,6 @@ #include "northbridge/amd/amdk8/reset_test.c" #include "superio/winbond/w83627hf/w83627hf_early_serial.c" -/* Used by ck804_early_setup(). */ -#define CK804_USE_NIC 1 -#define CK804_USE_ACI 1 - #include <cpu/amd/model_fxx_rev.h> #include <console/console.h> #include "northbridge/amd/amdk8/incoherent_ht.c" diff --git a/src/mainboard/msi/ms7260/Kconfig b/src/mainboard/msi/ms7260/Kconfig index 106db7b70b..a7f9e1afe6 100644 --- a/src/mainboard/msi/ms7260/Kconfig +++ b/src/mainboard/msi/ms7260/Kconfig @@ -8,6 +8,8 @@ config BOARD_SPECIFIC_OPTIONS # dummy select NORTHBRIDGE_AMD_AMDK8 select NORTHBRIDGE_AMD_AMDK8_ROOT_COMPLEX select SOUTHBRIDGE_NVIDIA_MCP55 + select MCP55_USE_NIC + select MCP55_USE_AZA select SUPERIO_WINBOND_W83627EHG select HAVE_BUS_CONFIG select HAVE_OPTION_TABLE diff --git a/src/mainboard/msi/ms7260/romstage.c b/src/mainboard/msi/ms7260/romstage.c index 762da8ced5..ebd54f4ef5 100644 --- a/src/mainboard/msi/ms7260/romstage.c +++ b/src/mainboard/msi/ms7260/romstage.c @@ -92,9 +92,6 @@ static inline int spd_read_byte(unsigned int device, unsigned int address) #include "resourcemap.c" #include "cpu/amd/dualcore/dualcore.c" -#define MCP55_NUM 1 -#define MCP55_USE_NIC 1 -#define MCP55_USE_AZA 1 #define MCP55_PCI_E_X_0 0 #define MCP55_MB_SETUP \ diff --git a/src/mainboard/msi/ms9282/romstage.c b/src/mainboard/msi/ms9282/romstage.c index 8935709323..8facf05f3a 100644 --- a/src/mainboard/msi/ms9282/romstage.c +++ b/src/mainboard/msi/ms9282/romstage.c @@ -105,7 +105,6 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "resourcemap.c" #include "cpu/amd/dualcore/dualcore.c" -#define MCP55_NUM 1 #include "southbridge/nvidia/mcp55/mcp55_early_setup_ss.h" //set GPIO to input mode #define MCP55_MB_SETUP \ diff --git a/src/mainboard/msi/ms9652_fam10/Kconfig b/src/mainboard/msi/ms9652_fam10/Kconfig index 7e0896536c..1404de8680 100644 --- a/src/mainboard/msi/ms9652_fam10/Kconfig +++ b/src/mainboard/msi/ms9652_fam10/Kconfig @@ -8,6 +8,8 @@ config BOARD_SPECIFIC_OPTIONS # dummy select DIMM_REGISTERED select NORTHBRIDGE_AMD_AMDFAM10 select SOUTHBRIDGE_NVIDIA_MCP55 + select MCP55_USE_NIC + select MCP55_USE_AZA select SUPERIO_WINBOND_W83627EHG select HAVE_BUS_CONFIG select HAVE_PIRQ_TABLE diff --git a/src/mainboard/msi/ms9652_fam10/romstage.c b/src/mainboard/msi/ms9652_fam10/romstage.c index a7dcaedb3d..b0696087df 100644 --- a/src/mainboard/msi/ms9652_fam10/romstage.c +++ b/src/mainboard/msi/ms9652_fam10/romstage.c @@ -89,10 +89,6 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "cpu/amd/quadcore/quadcore.c" -#define MCP55_NUM 1 -#define MCP55_USE_NIC 1 -#define MCP55_USE_AZA 1 - #define MCP55_PCI_E_X_0 1 #define MCP55_MB_SETUP \ diff --git a/src/mainboard/nvidia/l1_2pvv/Kconfig b/src/mainboard/nvidia/l1_2pvv/Kconfig index 1a260bf8e0..06e10ab92a 100644 --- a/src/mainboard/nvidia/l1_2pvv/Kconfig +++ b/src/mainboard/nvidia/l1_2pvv/Kconfig @@ -9,6 +9,8 @@ config BOARD_SPECIFIC_OPTIONS # dummy select NORTHBRIDGE_AMD_AMDK8 select NORTHBRIDGE_AMD_AMDK8_ROOT_COMPLEX select SOUTHBRIDGE_NVIDIA_MCP55 + select MCP55_USE_NIC + select MCP55_USE_AZA select SUPERIO_WINBOND_W83627EHG select HAVE_OPTION_TABLE select HAVE_BUS_CONFIG @@ -44,6 +46,10 @@ config MEM_TRAIN_SEQ int default 1 +config MCP55_NUM + int + default 2 + config SB_HT_CHAIN_ON_BUS0 int default 2 diff --git a/src/mainboard/nvidia/l1_2pvv/romstage.c b/src/mainboard/nvidia/l1_2pvv/romstage.c index dc76e0a32e..fc135d8378 100644 --- a/src/mainboard/nvidia/l1_2pvv/romstage.c +++ b/src/mainboard/nvidia/l1_2pvv/romstage.c @@ -100,10 +100,6 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "cpu/amd/dualcore/dualcore.c" -#define MCP55_NUM 2 -#define MCP55_USE_NIC 1 -#define MCP55_USE_AZA 1 - #define MCP55_PCI_E_X_0 2 #define MCP55_PCI_E_X_1 4 diff --git a/src/mainboard/sunw/ultra40/Kconfig b/src/mainboard/sunw/ultra40/Kconfig index ac07513fde..0c2a781332 100644 --- a/src/mainboard/sunw/ultra40/Kconfig +++ b/src/mainboard/sunw/ultra40/Kconfig @@ -14,6 +14,8 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_MP_TABLE select HAVE_HARD_RESET select BOARD_ROMSIZE_KB_1024 + select CK804_USE_NIC + select CK804_USE_ACI config MAINBOARD_DIR string diff --git a/src/mainboard/sunw/ultra40/romstage.c b/src/mainboard/sunw/ultra40/romstage.c index 86a194c735..992d0abde1 100644 --- a/src/mainboard/sunw/ultra40/romstage.c +++ b/src/mainboard/sunw/ultra40/romstage.c @@ -78,9 +78,6 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "cpu/amd/dualcore/dualcore.c" -#define CK804_USE_NIC 1 -#define CK804_USE_ACI 1 - #include "southbridge/nvidia/ck804/ck804_early_setup_ss.h" //set GPIO to input mode diff --git a/src/mainboard/supermicro/h8dme/Kconfig b/src/mainboard/supermicro/h8dme/Kconfig index cc16de0800..ab81031b07 100644 --- a/src/mainboard/supermicro/h8dme/Kconfig +++ b/src/mainboard/supermicro/h8dme/Kconfig @@ -9,6 +9,8 @@ config BOARD_SPECIFIC_OPTIONS # dummy select NORTHBRIDGE_AMD_AMDK8 select NORTHBRIDGE_AMD_AMDK8_ROOT_COMPLEX select SOUTHBRIDGE_NVIDIA_MCP55 + select MCP55_USE_NIC + select MCP55_USE_AZA select SUPERIO_WINBOND_W83627HF select HAVE_OPTION_TABLE select HAVE_BUS_CONFIG diff --git a/src/mainboard/supermicro/h8dme/romstage.c b/src/mainboard/supermicro/h8dme/romstage.c index 0d687032f1..55ec8cceca 100644 --- a/src/mainboard/supermicro/h8dme/romstage.c +++ b/src/mainboard/supermicro/h8dme/romstage.c @@ -155,10 +155,6 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "cpu/amd/dualcore/dualcore.c" -#define MCP55_NUM 1 -#define MCP55_USE_NIC 1 -#define MCP55_USE_AZA 1 - #define MCP55_PCI_E_X_0 4 #include "southbridge/nvidia/mcp55/mcp55_early_setup_ss.h" diff --git a/src/mainboard/supermicro/h8dmr/Kconfig b/src/mainboard/supermicro/h8dmr/Kconfig index 7aaad6014f..f7b0de4904 100644 --- a/src/mainboard/supermicro/h8dmr/Kconfig +++ b/src/mainboard/supermicro/h8dmr/Kconfig @@ -9,6 +9,8 @@ config BOARD_SPECIFIC_OPTIONS # dummy select NORTHBRIDGE_AMD_AMDK8 select NORTHBRIDGE_AMD_AMDK8_ROOT_COMPLEX select SOUTHBRIDGE_NVIDIA_MCP55 + select MCP55_USE_NIC + select MCP55_USE_AZA select SUPERIO_WINBOND_W83627HF select HAVE_OPTION_TABLE select HAVE_BUS_CONFIG diff --git a/src/mainboard/supermicro/h8dmr/romstage.c b/src/mainboard/supermicro/h8dmr/romstage.c index 3a3140d106..ccfce6e119 100644 --- a/src/mainboard/supermicro/h8dmr/romstage.c +++ b/src/mainboard/supermicro/h8dmr/romstage.c @@ -100,10 +100,6 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "cpu/amd/dualcore/dualcore.c" -#define MCP55_NUM 1 -#define MCP55_USE_NIC 1 -#define MCP55_USE_AZA 1 - #define MCP55_PCI_E_X_0 4 #include "southbridge/nvidia/mcp55/mcp55_early_setup_ss.h" diff --git a/src/mainboard/supermicro/h8dmr_fam10/Kconfig b/src/mainboard/supermicro/h8dmr_fam10/Kconfig index ca6001a57d..2d427e690b 100644 --- a/src/mainboard/supermicro/h8dmr_fam10/Kconfig +++ b/src/mainboard/supermicro/h8dmr_fam10/Kconfig @@ -8,6 +8,8 @@ config BOARD_SPECIFIC_OPTIONS # dummy select DIMM_REGISTERED select NORTHBRIDGE_AMD_AMDFAM10 select SOUTHBRIDGE_NVIDIA_MCP55 + select MCP55_USE_NIC + select MCP55_USE_AZA select SUPERIO_WINBOND_W83627HF select HAVE_BUS_CONFIG select HAVE_OPTION_TABLE diff --git a/src/mainboard/supermicro/h8dmr_fam10/romstage.c b/src/mainboard/supermicro/h8dmr_fam10/romstage.c index 61340cf2c6..846bc6e342 100644 --- a/src/mainboard/supermicro/h8dmr_fam10/romstage.c +++ b/src/mainboard/supermicro/h8dmr_fam10/romstage.c @@ -89,10 +89,6 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "cpu/amd/quadcore/quadcore.c" -#define MCP55_NUM 1 -#define MCP55_USE_NIC 1 -#define MCP55_USE_AZA 1 - #define MCP55_PCI_E_X_0 4 #include "southbridge/nvidia/mcp55/mcp55_early_setup_ss.h" diff --git a/src/mainboard/supermicro/h8qme_fam10/romstage.c b/src/mainboard/supermicro/h8qme_fam10/romstage.c index 4c1c486187..de7f7f2c7f 100644 --- a/src/mainboard/supermicro/h8qme_fam10/romstage.c +++ b/src/mainboard/supermicro/h8qme_fam10/romstage.c @@ -92,10 +92,6 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "cpu/amd/quadcore/quadcore.c" -#define MCP55_NUM 1 -#define MCP55_USE_NIC 0 -#define MCP55_USE_AZA 0 - #define MCP55_PCI_E_X_0 4 #include "southbridge/nvidia/mcp55/mcp55_early_setup_ss.h" diff --git a/src/mainboard/tyan/s2891/romstage.c b/src/mainboard/tyan/s2891/romstage.c index 7270384c7f..ad8e9767dd 100644 --- a/src/mainboard/tyan/s2891/romstage.c +++ b/src/mainboard/tyan/s2891/romstage.c @@ -62,12 +62,9 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "cpu/amd/dualcore/dualcore.c" -#define CK804_NUM 1 #include "southbridge/nvidia/ck804/ck804_early_setup_ss.h" #include "southbridge/nvidia/ck804/ck804_early_setup.c" - - #include "cpu/amd/car/post_cache_as_ram.c" #include "cpu/amd/model_fxx/init_cpus.c" diff --git a/src/mainboard/tyan/s2895/romstage.c b/src/mainboard/tyan/s2895/romstage.c index be170802b8..258e75f5fa 100644 --- a/src/mainboard/tyan/s2895/romstage.c +++ b/src/mainboard/tyan/s2895/romstage.c @@ -72,9 +72,6 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "cpu/amd/dualcore/dualcore.c" -#define CK804_USE_NIC 1 -#define CK804_USE_ACI 1 - #include "southbridge/nvidia/ck804/ck804_early_setup_ss.h" //set GPIO to input mode diff --git a/src/mainboard/tyan/s2912/Kconfig b/src/mainboard/tyan/s2912/Kconfig index 9af6e8f05a..4bed46fc8e 100644 --- a/src/mainboard/tyan/s2912/Kconfig +++ b/src/mainboard/tyan/s2912/Kconfig @@ -9,6 +9,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select NORTHBRIDGE_AMD_AMDK8 select NORTHBRIDGE_AMD_AMDK8_ROOT_COMPLEX select SOUTHBRIDGE_NVIDIA_MCP55 + select MCP55_USE_NIC select SUPERIO_WINBOND_W83627HF select HAVE_BUS_CONFIG select HAVE_OPTION_TABLE diff --git a/src/mainboard/tyan/s2912/romstage.c b/src/mainboard/tyan/s2912/romstage.c index c7078bbb34..4f048e8a05 100644 --- a/src/mainboard/tyan/s2912/romstage.c +++ b/src/mainboard/tyan/s2912/romstage.c @@ -100,9 +100,6 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "cpu/amd/dualcore/dualcore.c" -#define MCP55_NUM 1 -#define MCP55_USE_NIC 1 - #define MCP55_PCI_E_X_0 1 #define MCP55_MB_SETUP \ diff --git a/src/mainboard/tyan/s2912_fam10/Kconfig b/src/mainboard/tyan/s2912_fam10/Kconfig index 1f9ed0c3cd..55708f5a8d 100644 --- a/src/mainboard/tyan/s2912_fam10/Kconfig +++ b/src/mainboard/tyan/s2912_fam10/Kconfig @@ -8,6 +8,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select DIMM_REGISTERED select NORTHBRIDGE_AMD_AMDFAM10 select SOUTHBRIDGE_NVIDIA_MCP55 + select MCP55_USE_NIC select SUPERIO_WINBOND_W83627HF select HAVE_BUS_CONFIG select HAVE_OPTION_TABLE diff --git a/src/mainboard/tyan/s2912_fam10/romstage.c b/src/mainboard/tyan/s2912_fam10/romstage.c index d287dc4313..7094533b3c 100644 --- a/src/mainboard/tyan/s2912_fam10/romstage.c +++ b/src/mainboard/tyan/s2912_fam10/romstage.c @@ -89,9 +89,6 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "cpu/amd/quadcore/quadcore.c" -#define MCP55_NUM 1 -#define MCP55_USE_NIC 1 - #define MCP55_PCI_E_X_0 1 #define MCP55_MB_SETUP \ |