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authorJulius Werner <jwerner@chromium.org>2015-02-19 14:08:04 -0800
committerPatrick Georgi <pgeorgi@google.com>2015-04-21 08:21:15 +0200
commitd21a329866a1299b180f8b14b6c73bee3d754e57 (patch)
tree499483d184466d1aa71af356d46b6ab8c73b3082 /src/mainboard
parent24f94765311429d937befb4bebe1632eb683fd2c (diff)
downloadcoreboot-d21a329866a1299b180f8b14b6c73bee3d754e57.tar.xz
arm(64): Replace write32() and friends with writel()
This patch is a raw application of the following spatch to the directories src/arch/arm(64)?, src/mainboard/<arm(64)-board>, src/soc/<arm(64)-soc> and src/drivers/gic: @@ expression A, V; @@ - write32(V, A) + writel(V, A) @@ expression A, V; @@ - write16(V, A) + writew(V, A) @@ expression A, V; @@ - write8(V, A) + writeb(V, A) This replaces all uses of write{32,16,8}() with write{l,w,b}() which is currently equivalent and much more common. This is a preparatory step that will allow us to easier flip them all at once to the new write32(a,v) model. BRANCH=none BUG=chromium:451388 TEST=Compiled Cosmos, Daisy, Blaze, Pit, Ryu, Storm and Pinky. Change-Id: I16016cd77780e7cadbabe7d8aa7ab465b95b8f09 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 93f0ada19b429b4e30d67335b4e61d0f43597b24 Original-Change-Id: I1ac01c67efef4656607663253ed298ff4d0ef89d Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/254862 Reviewed-on: http://review.coreboot.org/9834 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/mainboard')
-rw-r--r--src/mainboard/cubietech/cubieboard/bootblock.c14
1 files changed, 7 insertions, 7 deletions
diff --git a/src/mainboard/cubietech/cubieboard/bootblock.c b/src/mainboard/cubietech/cubieboard/bootblock.c
index 360f914aa7..79d00189e8 100644
--- a/src/mainboard/cubietech/cubieboard/bootblock.c
+++ b/src/mainboard/cubietech/cubieboard/bootblock.c
@@ -38,12 +38,12 @@ static void cubieboard_set_sys_clock(void)
struct a10_ccm *ccm = (void *)A1X_CCM_BASE;
/* Switch CPU clock to main oscillator */
- write32(CPU_AHB_APB0_DEFAULT, &ccm->cpu_ahb_apb0_cfg);
+ writel(CPU_AHB_APB0_DEFAULT, &ccm->cpu_ahb_apb0_cfg);
/* Configure the PLL1. The value is the same one used by u-boot
* P = 1, N = 16, K = 1, M = 1 --> Output = 384 MHz
*/
- write32(0xa1005000, &ccm->pll1_cfg);
+ writel(0xa1005000, &ccm->pll1_cfg);
/* FIXME: Delay to wait for PLL to lock */
u32 wait = 1000;
@@ -53,7 +53,7 @@ static void cubieboard_set_sys_clock(void)
reg32 = read32(&ccm->cpu_ahb_apb0_cfg);
reg32 &= ~CPU_CLK_SRC_MASK;
reg32 |= CPU_CLK_SRC_PLL1;
- write32(reg32, &ccm->cpu_ahb_apb0_cfg);
+ writel(reg32, &ccm->cpu_ahb_apb0_cfg);
}
static void cubieboard_setup_clocks(void)
@@ -62,12 +62,12 @@ static void cubieboard_setup_clocks(void)
cubieboard_set_sys_clock();
/* Configure the clock source for APB1. This drives our UART */
- write32(APB1_CLK_SRC_OSC24M | APB1_RAT_N(0) | APB1_RAT_M(0),
- &ccm->apb1_clk_div_cfg);
+ writel(APB1_CLK_SRC_OSC24M | APB1_RAT_N(0) | APB1_RAT_M(0),
+ &ccm->apb1_clk_div_cfg);
/* Configure the clock for SD0 */
- write32(SDx_CLK_GATE | SDx_CLK_SRC_OSC24M | SDx_RAT_EXP_N(0)
- | SDx_RAT_M(1), &ccm->sd0_clk_cfg);
+ writel(SDx_CLK_GATE | SDx_CLK_SRC_OSC24M | SDx_RAT_EXP_N(0) | SDx_RAT_M(1),
+ &ccm->sd0_clk_cfg);
/* Enable clock to SD0 */
a1x_periph_clock_enable(A1X_CLKEN_MMC0);