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| author | zbao <fishbaozi@gmail.com> | 2012-07-23 19:41:03 +0800 |
|---|---|---|
| committer | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2012-07-25 01:18:03 +0200 |
| commit | d59d62484db7020c12438d2e7e308c81e46a4c9e (patch) | |
| tree | 24f42b2d458d5b2dad9556ad5b633c59b372735e /src/mainboard | |
| parent | 8d32b89fa4ea30aa57b578d79bc656c9e6545795 (diff) | |
| download | coreboot-d59d62484db7020c12438d2e7e308c81e46a4c9e.tar.xz | |
sync the northbridge.c with other family.
Change-Id: Ice4d0202590fca0169dcda2770ca6add166b5c13
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Signed-off-by: zbao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/1262
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'src/mainboard')
| -rw-r--r-- | src/mainboard/amd/parmer/devicetree.cb | 5 | ||||
| -rw-r--r-- | src/mainboard/amd/parmer/mainboard.c | 4 |
2 files changed, 5 insertions, 4 deletions
diff --git a/src/mainboard/amd/parmer/devicetree.cb b/src/mainboard/amd/parmer/devicetree.cb index 376e017c96..4a59b519be 100644 --- a/src/mainboard/amd/parmer/devicetree.cb +++ b/src/mainboard/amd/parmer/devicetree.cb @@ -25,7 +25,7 @@ chip northbridge/amd/agesa/family15tn/root_complex device pci_domain 0 on subsystemid 0x1022 0x1410 inherit chip northbridge/amd/agesa/family15tn # CPU side of HT root complex -# device pci 18.0 on # northbridge + device pci 18.0 on # northbridge chip northbridge/amd/agesa/family15tn # PCI side of HT root complex device pci 0.0 on end # Root Complex device pci 1.0 on end # Internal Graphics P2P bridge 0x9804 @@ -37,6 +37,7 @@ chip northbridge/amd/agesa/family15tn/root_complex device pci 6.0 on end # PCIE Slot1 x1 device pci 7.0 on end # LAN device pci 8.0 off end # NB/SB Link P2P bridge + end end chip southbridge/amd/agesa/hudson # it is under NB/SB Link, but on the same pci bus device pci 10.0 on end # XHCI HC0 @@ -74,7 +75,7 @@ chip northbridge/amd/agesa/family15tn/root_complex register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE register "gpp_configuration" = "4" end #southbridge/amd/hudson - device pci 18.0 on end +# device pci 18.0 on end #device pci 18.0 on end device pci 18.1 on end device pci 18.2 on end diff --git a/src/mainboard/amd/parmer/mainboard.c b/src/mainboard/amd/parmer/mainboard.c index b16be363c7..bf04d302ce 100644 --- a/src/mainboard/amd/parmer/mainboard.c +++ b/src/mainboard/amd/parmer/mainboard.c @@ -55,8 +55,8 @@ int add_mainboard_resources(struct lb_memory *mem) /* UMA is removed from system memory in the northbridge code, but * in some circumstances we want the memory mentioned as reserved. */ - /* TODO: Check out why it is commented. */ -#if 0 /* (CONFIG_GFXUMA == 1) */ + /* TODO: Check out why it was commented. */ +#if CONFIG_GFXUMA printk(BIOS_INFO, "uma_memory_start=0x%llx, uma_memory_size=0x%llx \n", uma_memory_base, uma_memory_size); lb_add_memory_range(mem, LB_MEM_RESERVED, uma_memory_base, |