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| author | Wisley Chen <wisley.chen@quantatw.com> | 2020-10-14 16:25:11 +0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-10-19 06:48:44 +0000 |
| commit | f580d9ffef93243509e84d558e42a8722d0ad6e7 (patch) | |
| tree | 25ee7fd56443df231e308798ad60b7c2433f6e72 /src/mainboard | |
| parent | 42aa2cb94ab0b7fefc8204fcf128f6953af00b9a (diff) | |
| download | coreboot-f580d9ffef93243509e84d558e42a8722d0ad6e7.tar.xz | |
mb/google/volteer/elemi: Add memory.c for DDR4
Add new memory.c to support DDR4 memory types.
BUG=b:170604353
TEST=emerge-volteer coreboot chromeos-bootimage
Change-Id: If96b0bda0ce95766f0957c37aa7cbecefc9c03e0
Signed-off-by: Wisley Chen <wisley.chen@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46378
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Diffstat (limited to 'src/mainboard')
| -rw-r--r-- | src/mainboard/google/volteer/variants/elemi/Makefile.inc | 3 | ||||
| -rw-r--r-- | src/mainboard/google/volteer/variants/elemi/memory.c | 31 |
2 files changed, 34 insertions, 0 deletions
diff --git a/src/mainboard/google/volteer/variants/elemi/Makefile.inc b/src/mainboard/google/volteer/variants/elemi/Makefile.inc new file mode 100644 index 0000000000..9064208bff --- /dev/null +++ b/src/mainboard/google/volteer/variants/elemi/Makefile.inc @@ -0,0 +1,3 @@ +# SPDX-License-Identifier: GPL-2.0-only + +romstage-y += memory.c diff --git a/src/mainboard/google/volteer/variants/elemi/memory.c b/src/mainboard/google/volteer/variants/elemi/memory.c new file mode 100644 index 0000000000..d3de4be711 --- /dev/null +++ b/src/mainboard/google/volteer/variants/elemi/memory.c @@ -0,0 +1,31 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/gpio.h> +#include <baseboard/variants.h> +#include <gpio.h> + +/*This mb_ddr4_cfg structure is intentionally left empty so that fields are left nil. */ +static const struct mb_ddr4_cfg elemi_memcfg = { +}; + +static const struct ddr_memory_cfg baseboard_memcfg = { + .mem_type = MEMTYPE_DDR4, + .ddr4_cfg = &elemi_memcfg +}; + +const struct ddr_memory_cfg *variant_memory_params(void) +{ + return &baseboard_memcfg; +} + +int variant_memory_sku(void) +{ + gpio_t spd_gpios[] = { + GPIO_MEM_CONFIG_3, + GPIO_MEM_CONFIG_2, + GPIO_MEM_CONFIG_1, + GPIO_MEM_CONFIG_0, + }; + + return gpio_base2_value(spd_gpios, ARRAY_SIZE(spd_gpios)); +} |