google/lars,lili: Update GPIO mapping

Combination of several commits from Chromium tree:
949037c [Lars: coreboot GPIO changes for EVT]
c286789 [Lars: Set USB Type A current limit to 2A]
0f1b26d [lars: set BOOT BEEP GPIO GPP_F_23 to output and Low]
4a0650d [Lili: Support touchscreen]

Disable unused GPIOs based on schematic and
adds GPIO mappings for HSJ_MIC_DET, PCH_BUZZER and AUDIO_INT_WAK.

Set GPIOs USB_A0_ILIM_SEL & USB_A1_ILIM_SEL low to enable 2A
charging from the USB Type-A port.

GPP_F_23 is set to NC currently and is floating, causing the on-board
speaker to have no audio or the audio has noise; set to output/low.

These commits bring lars' GPIO mapping in line with the Chromium tree.

Original-Change-Id: I3bf4aa8599255e5382d99810b4c83b4c97c648b6
Original-Change-Id: I328a8be22dc59492477cbe362a5d5b94aa80a397
Original-Change-Id: I253e55bf2b423363a00347778cabaa4184d85aec
Original-Change-Id: I761f7c5ea5fc7a173c07a8c37da1338a1b2cd269
Original-Signed-off-by: David Wu <David_Wu@quantatw.com>
Original-Signed-off-by: Naresh G Solanki <Naresh.Solanki@intel.com>
Original-Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Original-Reviewed-by: Shobhit Srivastava <shobhit.srivastava@intel.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: David Wu <david_wu@quantatw.com>
Original-Tested-by: Balaji Manigandan <balaji.manigandan@intel.com>
Original-Tested-by: Kuen Liu <kuen.liu@quantatw.com>

Change-Id: Ic2d188fbf913a11fbf6ad1f0eb3a5e72ba4cb1cf
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/23571
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

1 files changed, 62 insertions, 62 deletions

diff --git a/src/mainboard/google/lars/gpio.h b/src/mainboard/google/lars/gpio.h
index 77151a4b9e..a05c7022d8 100644
--- a/src/mainboard/google/lars/gpio.h
+++ b/src/mainboard/google/lars/gpio.h
@@ -63,14 +63,14 @@ static const struct pad_config gpio_table[] = {
 /* LPC_LAD_3 */		PAD_CFG_NF(GPP_A4, 20K_PU, DEEP, NF1),
 /* LPC_FRAME */		PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1),
 /* LPC_SERIRQ */	PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1),
-/* PIRQA# */		/* GPP_A7 */
+/* PIRQA# */		PAD_CFG_NC(GPP_A7),
 /* LPC_CLKRUN */	PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1),
 /* EC_LPC_CLK */	PAD_CFG_NF(GPP_A9, NONE, DEEP, NF1),
-/* PCH_LPC_CLK */	/* GPP_A10 */
-/* EC_HID_INT */	/* GPP_A11 */
-/* ISH_KB_PROX_INT */	PAD_CFG_GPO(GPP_A12, 0, DEEP),
+/* PCH_LPC_CLK */	PAD_CFG_NC(GPP_A10),
+/* EC_HID_INT */	PAD_CFG_NC(GPP_A11),
+/* ISH_KB_PROX_INT */	PAD_CFG_NC(GPP_A12),
 /* PCH_SUSPWRACB */	PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1),
-/* PM_SUS_STAT */	PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1),
+/* PM_SUS_STAT */	PAD_CFG_NC(GPP_A14),
 /* PCH_SUSACK */	PAD_CFG_NF(GPP_A15, NONE, DEEP, NF1),
 /* SD_1P8_SEL */	PAD_CFG_NC(GPP_A16),
 /* SD_PWR_EN */		PAD_CFG_NC(GPP_A17),
@@ -87,35 +87,35 @@ static const struct pad_config gpio_table[] = {
 /* BT_RF_KILL */	PAD_CFG_NC(GPP_B4),
 /* SRCCLKREQ0# */	PAD_CFG_GPI_ACPI_SCI(GPP_B5, NONE, DEEP, YES), /* TOUCHPAD WAKE */
 /* WIFI_CLK_REQ */	PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1),
-/* KEPLR_CLK_REQ */	PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1),
-/* SRCCLKREQ3# */	/* GPP_B8 */
-/* SSD_CLK_REQ */	PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1),
-/* SRCCLKREQ5# */	/* GPP_B10 */
-/* MPHY_EXT_PWR_GATE */	PAD_CFG_NF(GPP_B11, NONE, DEEP, NF1),
+/* KEPLR_CLK_REQ */	PAD_CFG_NC(GPP_B7),
+/* AUDIO_INT_WAK */	PAD_CFG_GPI_ACPI_SCI(GPP_B8, NONE, DEEP, YES),
+/* SSD_CLK_REQ */	PAD_CFG_NC(GPP_B9),
+/* SRCCLKREQ5# */	PAD_CFG_NC(GPP_B10),
+/* MPHY_EXT_PWR_GATE */ PAD_CFG_NC(GPP_B11),
 /* PM_SLP_S0 */		PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1),
 /* PCH_PLT_RST */	PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),
-/* GPP_B_14_SPKR */	PAD_CFG_GPI_GPIO_DRIVER(GPP_B14, NONE, DEEP),
-/* GSPI0_CS# */		/* GPP_B15 */
+/* PCH_BUZZER */	PAD_CFG_GPO(GPP_B14, 0, DEEP),
+/* GSPI0_CS# */		PAD_CFG_NC(GPP_B15),
 /* WLAN_PCIE_WAKE */	PAD_CFG_GPI_ACPI_SCI(GPP_B16, NONE, DEEP, YES),
-/* SSD_PCIE_WAKE */	PAD_CFG_GPI_GPIO_DRIVER(GPP_B17, NONE, DEEP),
-/* GSPI0_MOSI */	/* GPP_B18 */
-/* CCODEC_SPI_CS */	PAD_CFG_NF(GPP_B19, NONE, DEEP, NF1),
-/* CODEC_SPI_CLK */	PAD_CFG_NF(GPP_B20, NONE, DEEP, NF1),
-/* CODEC_SPI_MISO */	PAD_CFG_NF(GPP_B21, NONE, DEEP, NF1),
-/* CODEC_SPI_MOSI */	PAD_CFG_NF(GPP_B22, NONE, DEEP, NF1),
-/* SM1ALERT# */		PAD_CFG_GPO(GPP_B23, 0, DEEP),
+/* SSD_PCIE_WAKE */	PAD_CFG_NC(GPP_B17),
+/* GSPI0_MOSI */	PAD_CFG_NC(GPP_B18),
+/* CCODEC_SPI_CS */	PAD_CFG_NC(GPP_B19),
+/* CODEC_SPI_CLK */	PAD_CFG_NC(GPP_B20),
+/* CODEC_SPI_MISO */	PAD_CFG_NC(GPP_B21),
+/* CODEC_SPI_MOSI */	PAD_CFG_NC(GPP_B22),
+/* SM1ALERT# */		PAD_CFG_NC(GPP_B23),
 /* SMB_CLK */		PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1),
 /* SMB_DATA */		PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1),
 /* SMBALERT# */		PAD_CFG_GPO(GPP_C2, 0, DEEP),
-/* M2_WWAN_PWREN */	PAD_CFG_GPO(GPP_C3, 0, DEEP),
-/* SML0DATA */		PAD_CFG_GPI_GPIO_DRIVER(GPP_C4, NONE, DEEP),
-/* SML0ALERT# */	PAD_CFG_GPO(GPP_C5, 0, DEEP),
+/* M2_WWAN_PWREN */	PAD_CFG_NC(GPP_C3),
+/* SML0DATA */		PAD_CFG_NC(GPP_C4),
+/* SML0ALERT# */	PAD_CFG_NC(GPP_C5),
 /* EC_IN_RW */		PAD_CFG_GPI_GPIO_DRIVER(GPP_C6, NONE, DEEP),
-/* USB_CTL */		PAD_CFG_GPO(GPP_C7, 1, DEEP),
-/* UART0_RXD */		/* GPP_C8 */
-/* UART0_TXD */		/* GPP_C9 */
-/* NFC_RST* */		PAD_CFG_GPO(GPP_C10, 0, DEEP),
-/* EN_PP3300_KEPLER */	PAD_CFG_TERM_GPO(GPP_C11, 0, 20K_PD, DEEP),
+/* USB_CTL */		PAD_CFG_NC(GPP_C7),
+/* UART0_RXD */		PAD_CFG_NC(GPP_C8),
+/* UART0_TXD */		PAD_CFG_NC(GPP_C9),
+/* NFC_RST* */		PAD_CFG_NC(GPP_C10),
+/* EN_PP3300_KEPLER */	PAD_CFG_NC(GPP_C11),
 /* PCH_MEM_CFG0 */	PAD_CFG_GPI_GPIO_DRIVER(GPP_C12, NONE, DEEP),
 /* PCH_MEM_CFG1 */	PAD_CFG_GPI_GPIO_DRIVER(GPP_C13, NONE, DEEP),
 /* PCH_MEM_CFG2 */	PAD_CFG_GPI_GPIO_DRIVER(GPP_C14, NONE, DEEP),
@@ -128,29 +128,29 @@ static const struct pad_config gpio_table[] = {
 /* GD_UART2_TXD */	PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1),
 /* TCH_PNL_PWREN */	PAD_CFG_GPO(GPP_C22, 1, DEEP),
 /* SPI_WP_STATUS */	PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, 20K_PU, DEEP),
-/* ITCH_SPI_CS */	/* GPP_D0 */
-/* ITCH_SPI_CLK */	/* GPP_D1 */
-/* ITCH_SPI_MISO_1 */	/* GPP_D2 */
-/* ITCH_SPI_MISO_0 */	/* GPP_D3 */
-/* CAM_FLASH_STROBE */	PAD_CFG_NF(GPP_D4, NONE, DEEP, NF1),
-/* EN_PP3300_DX_EMMC */	PAD_CFG_GPO(GPP_D5, 1, DEEP),
-/* EN_PP1800_DX_EMMC */	PAD_CFG_GPO(GPP_D6, 1, DEEP),
-/* SH_I2C1_SDA */	PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1),
-/* SH_I2C1_SCL */	PAD_CFG_NF(GPP_D8, NONE, DEEP, NF1),
-			PAD_CFG_GPO(GPP_D9, 0, DEEP),
-/* USB_A0_ILIM_SEL */	PAD_CFG_GPO(GPP_D10, 1, DEEP),
-/* USB_A1_ILIM_SEL */	PAD_CFG_GPO(GPP_D11, 1, DEEP),
-/* EN_PP3300_DX_CAM */	PAD_CFG_GPO(GPP_D12, 1, DEEP),
+/* ITCH_SPI_CS */	PAD_CFG_NC(GPP_D0),
+/* ITCH_SPI_CLK */	PAD_CFG_NC(GPP_D1),
+/* ITCH_SPI_MISO_1 */	PAD_CFG_NC(GPP_D2),
+/* ITCH_SPI_MISO_0 */	PAD_CFG_NC(GPP_D3),
+/* CAM_FLASH_STROBE */	PAD_CFG_NC(GPP_D4),
+/* EN_PP3300_DX_EMMC */ PAD_CFG_NC(GPP_D5),
+/* EN_PP1800_DX_EMMC */ PAD_CFG_NC(GPP_D6),
+/* SH_I2C1_SDA */	PAD_CFG_NC(GPP_D7),
+/* SH_I2C1_SCL */	PAD_CFG_NC(GPP_D8),
+/* ISH_SPI_CSB */	PAD_CFG_NC(GPP_D9),
+/* USB_A0_ILIM_SEL */	PAD_CFG_GPO(GPP_D10, 0, DEEP),
+/* USB_A1_ILIM_SEL */	PAD_CFG_GPO(GPP_D11, 0, DEEP),
+/* EN_PP3300_DX_CAM */	PAD_CFG_NC(GPP_D12),
 /* EN_PP1800_DX_AUDIO */PAD_CFG_GPO(GPP_D13, 1, DEEP),
-/* ISH_UART0_TXD */	/* GPP_D14 */
-/* ISH_UART0_RTS */	/* GPP_D15 */
-/* ISH_UART0_CTS */	/* GPP_D16 */
+/* ISH_UART0_TXD */	PAD_CFG_NC(GPP_D14),
+/* ISH_UART0_RTS */	PAD_CFG_NC(GPP_D15),
+/* ISH_UART0_CTS */	PAD_CFG_NC(GPP_D16),
 /* DMIC_CLK_1 */	PAD_CFG_NF(GPP_D17, NONE, DEEP, NF1),
 /* DMIC_DATA_1 */	PAD_CFG_NF(GPP_D18, NONE, DEEP, NF1),
 /* DMIC_CLK_0 */	PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1),
 /* DMIC_DATA_0 */	PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1),
-/* ITCH_SPI_D2 */	/* GPP_D21 */
-/* ITCH_SPI_D3 */	/* GPP_D22 */
+/* ITCH_SPI_D2 */	PAD_CFG_NC(GPP_D21),
+/* ITCH_SPI_D3 */	PAD_CFG_NC(GPP_D22),
 /* I2S_MCLK */		PAD_CFG_NF(GPP_D23, NONE, DEEP, NF1),
 /* SPI_TPM_IRQ */	PAD_CFG_GPI_APIC(GPP_E0, NONE, PLTRST),
 /* SATAXPCIE1 */	PAD_CFG_NC(GPP_E1),
@@ -159,7 +159,7 @@ static const struct pad_config gpio_table[] = {
 /* SSD_SATA_DEVSLP */	PAD_CFG_NC(GPP_E4),
 /* SATA_DEVSLP1 */	PAD_CFG_NC(GPP_E5),
 /* SATA_DEVSLP2 */	PAD_CFG_NC(GPP_E6),
-/* TCH_PNL_INTR* */	PAD_CFG_NC(GPP_E7),
+/* TCH_PNL_INTR* */	PAD_CFG_GPI_APIC(GPP_E7, NONE, PLTRST),
 /* SATALED# */		PAD_CFG_NC(GPP_E8),
 /* USB2_OC_0 */		PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1),
 /* USB2_OC_1 */		PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1),
@@ -174,7 +174,7 @@ static const struct pad_config gpio_table[] = {
 /* DDPB_CTRLDATA */	PAD_CFG_NF(GPP_E19, NONE, DEEP, NF1),
 /* DDPC_CTRLCLK */	PAD_CFG_NF(GPP_E20, NONE, DEEP, NF1),
 /* DDPC_CTRLDATA */	PAD_CFG_NF(GPP_E21, NONE, DEEP, NF1),
-/* DDPD_CTRLCLK */	PAD_CFG_GPI_GPIO_DRIVER(GPP_E22, NONE, DEEP),
+/* DDPD_CTRLCLK */	PAD_CFG_NC(GPP_E22),
 /* TCH_PNL_RST */	PAD_CFG_GPO(GPP_E23, 1, DEEP),
 /* I2S2_SCLK */		PAD_CFG_GPI_GPIO_DRIVER(GPP_F0, NONE, DEEP),
 /* I2S2_SFRM */		PAD_CFG_GPI_GPIO_DRIVER(GPP_F1, NONE, DEEP),
@@ -182,8 +182,8 @@ static const struct pad_config gpio_table[] = {
 /* I2S2_RXD */		PAD_CFG_GPI_GPIO_DRIVER(GPP_F3, NONE, DEEP),
 /* I2C2_SDA */		PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1),
 /* I2C2_SCL */		PAD_CFG_NF(GPP_F5, NONE, DEEP, NF1),
-/* I2C3_SDA */		/* GPP_F6 */
-/* I2C3_SCL */		/* GPP_F7 */
+/* I2C3_SDA */		PAD_CFG_NC(GPP_F6),
+/* I2C3_SCL */		PAD_CFG_NC(GPP_F7),
 /* I2C4_SDA */		PAD_CFG_NF_1V8(GPP_F8, NONE, DEEP, NF1),
 /* I2C4_SCL */		PAD_CFG_NF_1V8(GPP_F9, NONE, DEEP, NF1),
 /* AUDIO_IRQ */		PAD_CFG_GPI_APIC(GPP_F10, NONE, PLTRST),
@@ -199,15 +199,15 @@ static const struct pad_config gpio_table[] = {
 /* EMMC_DATA7 */	PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1),
 /* EMMC_RCLK */		PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1),
 /* EMMC_CLK */		PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1),
-			/* GPP_F23 */
-/* SD_CMD */		/* GPP_G0 */
-/* SD_DATA0 */		/* GPP_G1 */
-/* SD_DATA1 */		/* GPP_G2 */
-/* SD_DATA2 */		/* GPP_G3 */
-/* SD_DATA3 */		/* GPP_G4 */
-/* SD_CD# */		/* GPP_G5 */
-/* SD_CLK */		/* GPP_G6 */
-/* SD_WP */		/* GPP_G7 */
+/* BOOT_BEEP */		PAD_CFG_GPO(GPP_F23, 0, DEEP),
+/* SD_CMD */		PAD_CFG_NC(GPP_G0),
+/* SD_DATA0 */		PAD_CFG_NC(GPP_G1),
+/* SD_DATA1 */		PAD_CFG_NC(GPP_G2),
+/* SD_DATA2 */		PAD_CFG_NC(GPP_G3),
+/* SD_DATA3 */		PAD_CFG_NC(GPP_G4),
+/* SD_CD# */		PAD_CFG_NC(GPP_G5),
+/* SD_CLK */		PAD_CFG_NC(GPP_G6),
+/* SD_WP */		PAD_CFG_NC(GPP_G7),
 /* PCH_BATLOW */	PAD_CFG_NF(GPD0, NONE, DEEP, NF1),
 /* EC_PCH_ACPRESENT */	PAD_CFG_NF(GPD1, NONE, DEEP, NF1),
 /* EC_PCH_WAKE */	PAD_CFG_NF(GPD2, NONE, DEEP, NF1),
@@ -215,11 +215,11 @@ static const struct pad_config gpio_table[] = {
 /* PM_SLP_S3# */	PAD_CFG_NF(GPD4, NONE, DEEP, NF1),
 /* PM_SLP_S4# */	PAD_CFG_NF(GPD5, NONE, DEEP, NF1),
 /* PM_SLP_SA# */	PAD_CFG_NF(GPD6, NONE, DEEP, NF1),
-			/* GPD7 */
+/* GPD7 */		PAD_CFG_NC(GPD7),
 /* PM_SUSCLK */		PAD_CFG_NF(GPD8, NONE, DEEP, NF1),
-/* PCH_SLP_WLAN# */	/* GPD9 */
-/* PM_SLP_S5# */	PAD_CFG_NF(GPD10, NONE, DEEP, NF1),
-/* LANPHYC */		/* GPD11 */
+/* PCH_SLP_WLAN# */	PAD_CFG_NC(GPD9),
+/* PM_SLP_S5# */	PAD_CFG_NC(GPD10),
+/* LANPHYC */		PAD_CFG_NC(GPD11),
 };
 
 /* Early pad configuration in romstage. */