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authorKevin Chiu <Kevin.Chiu@quantatw.com>2018-08-03 18:52:18 +0800
committerMartin Roth <martinroth@google.com>2018-08-09 15:47:45 +0000
commit089b6857615a3bbf9c28b8e658da6b768650692f (patch)
tree948fa130c8730c3951228d0a2b261fa32436da4f /src/mainboard
parentd87a9b8e67105b29e0f54b99e4322c4090a925c4 (diff)
downloadcoreboot-089b6857615a3bbf9c28b8e658da6b768650692f.tar.xz
google/grunt: Override BayHub EMMC driving strength
Careena EVT SanDisk EMMC sku has high fail rate of 0x5B reboot failure. It'll need to increase 1.8V EMMC CLK/CMD, Data driving strength for this issue. CLK[6:4] CMD,DATA[3:1] original register value: 0x6B enhanced: 0x7F BUG=b:111964336 BRANCH=master TEST=emerge-grunt coreboot Change-Id: I3db38ff12c566c258895c6643008a0472ca528bb Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/27816 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard')
-rw-r--r--src/mainboard/google/kahlee/variants/baseboard/mainboard.c26
1 files changed, 25 insertions, 1 deletions
diff --git a/src/mainboard/google/kahlee/variants/baseboard/mainboard.c b/src/mainboard/google/kahlee/variants/baseboard/mainboard.c
index 54743ef7c1..b1bd4928d2 100644
--- a/src/mainboard/google/kahlee/variants/baseboard/mainboard.c
+++ b/src/mainboard/google/kahlee/variants/baseboard/mainboard.c
@@ -17,7 +17,8 @@
#include <baseboard/variants.h>
#include <gpio.h>
#include <variant/gpio.h>
-
+#include <device/pci.h>
+#include <drivers/generic/bayhub/bh720.h>
uint8_t variant_board_sku(void)
{
@@ -36,3 +37,26 @@ void variant_mainboard_suspend_resume(void)
gpio_set(GPIO_133, 0);
}
#endif
+
+void bh720_driving_strength(struct device *dev)
+{
+ u32 sdbar;
+ u32 bh720_pcr_data;
+
+ sdbar = pci_read_config32(dev, PCI_BASE_ADDRESS_1);
+
+ /* Enable Memory Access Function */
+ write32((void *)(sdbar + BH720_MEM_ACCESS_EN), 0x40000000);
+ write32((void *)(sdbar + BH720_MEM_RW_DATA), 0x80000000);
+ write32((void *)(sdbar + BH720_MEM_RW_ADR), 0x800000D0);
+
+ /* Read current EMMC 1.8V CLK/DATA,CMD driving strength */
+ write32((void *)(sdbar + BH720_MEM_RW_ADR), 0x40000304);
+ bh720_pcr_data = read32((void *)(sdbar + BH720_MEM_RW_DATA));
+
+ /* set EMMC 1.8V CLK/DATA,CMD the max level */
+ write32((void *)(sdbar + BH720_MEM_RW_DATA),
+ bh720_pcr_data | (BH720_PCR_CLK_DRV_MAX << 4) |
+ (BH720_PCR_DATA_CMD_DRV_MAX << 1));
+ write32((void *)(sdbar + BH720_MEM_RW_ADR), 0x80000304);
+}