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| author | Kevin Chiu <Kevin.Chiu@quantatw.com> | 2020-04-28 23:19:40 +0800 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2020-05-10 20:34:41 +0000 |
| commit | 137c5c475980a660f4968f231b0f8a62f30575b1 (patch) | |
| tree | 97be1bbc1e17c1a48b6720b836effc77398c0d4d /src/mainboard | |
| parent | 5ee19cda8136a877c9ec1433eb805b220c219c42 (diff) | |
| download | coreboot-137c5c475980a660f4968f231b0f8a62f30575b1.tar.xz | |
mb/google/kahlee: Hold WLAN PCIe reset low at boot for mordin
gpio70 is assigned to use as WLAN rst in new schematic to fulfill
RTK RTL8822CE power sequence:
WLAN rst will need to be active at least 50ms after WLAN power on.
Also in order to keep the rst low in consistency, override default
gpio70 to low.
BUG=b:154357210,b:154848243
BRANCH=master
TEST=emerge-grunt coreboot
Change-Id: I98c8afe42b7f92016f83483acbb3b9ae64b159f7
Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40805
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard')
| -rw-r--r-- | src/mainboard/google/kahlee/variants/careena/Makefile.inc | 1 | ||||
| -rw-r--r-- | src/mainboard/google/kahlee/variants/careena/variant.c | 24 |
2 files changed, 25 insertions, 0 deletions
diff --git a/src/mainboard/google/kahlee/variants/careena/Makefile.inc b/src/mainboard/google/kahlee/variants/careena/Makefile.inc index dcd7d302a4..60da7f361b 100644 --- a/src/mainboard/google/kahlee/variants/careena/Makefile.inc +++ b/src/mainboard/google/kahlee/variants/careena/Makefile.inc @@ -6,6 +6,7 @@ subdirs-y += ./spd +bootblock-y += variant.c romstage-y += variant.c ramstage-y += ../baseboard/mainboard.c diff --git a/src/mainboard/google/kahlee/variants/careena/variant.c b/src/mainboard/google/kahlee/variants/careena/variant.c index e0bd5d170c..e5a05acca1 100644 --- a/src/mainboard/google/kahlee/variants/careena/variant.c +++ b/src/mainboard/google/kahlee/variants/careena/variant.c @@ -4,10 +4,24 @@ #include <ec/google/chromeec/ec.h> #include <baseboard/variants.h> #include <variant/sku.h> +#include <gpio.h> +#include <variant/gpio.h> + +static const struct soc_amd_gpio variant_gpio_wlan_rst_early_reset[] = { + /* GPIO_70 - WLAN_PE_RST_L */ + PAD_GPO(GPIO_70, LOW), +}; + +const struct soc_amd_gpio *variant_wlan_rst_early_gpio_table(size_t *size) +{ + *size = ARRAY_SIZE(variant_gpio_wlan_rst_early_reset); + return variant_gpio_wlan_rst_early_reset; +} void variant_romstage_entry(int s3_resume) { uint32_t sku = google_chromeec_get_sku_id(); + uint32_t bid; if (!s3_resume) { /* Based on SKU, turn on keyboard backlight */ @@ -23,4 +37,14 @@ void variant_romstage_entry(int s3_resume) break; } } + + google_chromeec_get_board_version(&bid); + + if (bid == 7) + /* + * Config WLAN RST - GPIO70 PU: release RST + * From RTK RTL8822CE spec, WLAN RST needs to be active + * at least 50 ms since WLAN power on + */ + gpio_set(GPIO_70, 1); } |