soc/qualcomm/ipq40xx: Add support for BLSP QUP I2C

Able to talk to the TPM device and the commands
seem to succeed.

BUG=chrome-os-partner:49249 chrome-os-partner:49250
TEST=All commands to the TPM succeed
BRANCH=none

Original-Commit-Id: c13900108f524c8422c38dee88469c8bfe24d0bd
Original-Change-Id: Ie8c3c1ab1290cd8d7e6ddd1ae22f765c7be81019
Original-Signed-off-by: Varadarajan Narayanan <varada@codeaurora.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/333314
Original-Commit-Ready: David Hendricks <dhendrix@chromium.org>
Original-Tested-by: David Hendricks <dhendrix@chromium.org>
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>

squashed:

soc/qualcomm/ipq40xx: Add support for BLSP QUP SPI

- Enable BLSP SPI driver for ipq40xx
- supports only FIFO mode

BUG=chrome-os-partner:49249
TEST=None. Initial code not sure if it will even compile
BRANCH=none

Original-Commit-Id: 0714025975854dd048d35fe602824ead4c7d94e9
Original-Change-Id: If809b0fdf7d6c9405db6fd3747a3774c00ea9870
Original-Signed-off-by: Varadarajan Narayanan <varada@codeaurora.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/333303
Original-Commit-Ready: David Hendricks <dhendrix@chromium.org>
Original-Tested-by: David Hendricks <dhendrix@chromium.org>
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>

Change-Id: Ia518af5bfc782b08a0883ac93224d476d07e2426
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/14677
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

5 files changed, 41 insertions, 27 deletions

diff --git a/src/mainboard/google/gale/Kconfig b/src/mainboard/google/gale/Kconfig
index 6888e41ce5..b839fb45a1 100644
--- a/src/mainboard/google/gale/Kconfig
+++ b/src/mainboard/google/gale/Kconfig
@@ -56,7 +56,7 @@ config DRAM_SIZE_MB
 
 config DRIVER_TPM_I2C_BUS
 	hex
-	default 0x1
+	default 0x2
 
 config DRIVER_TPM_I2C_ADDR
 	hex
diff --git a/src/mainboard/google/gale/Makefile.inc b/src/mainboard/google/gale/Makefile.inc
index 491b5b5075..7ce1e0d38d 100644
--- a/src/mainboard/google/gale/Makefile.inc
+++ b/src/mainboard/google/gale/Makefile.inc
@@ -21,7 +21,7 @@ bootblock-y += reset.c
 verstage-y += boardid.c
 verstage-y += cdp.c
 verstage-y += chromeos.c
-verstage-y += gsbi.c
+verstage-y += blsp.c
 verstage-y += memlayout.ld
 verstage-y += reset.c
 
diff --git a/src/mainboard/google/gale/gsbi.c b/src/mainboard/google/gale/blsp.c
index 915f317df9..3be075f141 100644
--- a/src/mainboard/google/gale/gsbi.c
+++ b/src/mainboard/google/gale/blsp.c
@@ -27,34 +27,47 @@
  * SUCH DAMAGE.
  */
 
+#include <gpio.h>
 #include <soc/gpio.h>
-#include <soc/gsbi.h>
+#include <soc/blsp.h>
 #include <soc/qup.h>
 
-#define GPIO_FUNC_I2C		0x1
+#define IPQ40XX_I2C0_PINGROUP_1		1
+#define IPQ40XX_I2C0_PINGROUP_2		(!IPQ40XX_I2C0_PINGROUP_1)
 
-int gsbi_init_board(gsbi_id_t gsbi_id)
+#if IPQ40XX_I2C0_PINGROUP_1
+
+#define SCL_GPIO		20
+#define SDA_GPIO		21
+#define GPIO_FUNC_SCL		0x1
+#define GPIO_FUNC_SDA		0x1
+
+#elif IPQ40XX_I2C0_PINGROUP_2
+
+#define SCL_GPIO		58
+#define SDA_GPIO		59
+#define GPIO_FUNC_SCL		0x3
+#define GPIO_FUNC_SDA		0x2
+
+#else
+
+#warning "TPM: I2C pingroup not specified"
+
+#endif
+
+int blsp_i2c_init_board(blsp_qup_id_t id)
 {
-	switch (gsbi_id) {
-	case GSBI_ID_7:
-			gpio_tlmm_config_set(8, GPIO_FUNC_I2C,
-					     GPIO_NO_PULL, GPIO_2MA, 1);
-			gpio_tlmm_config_set(9, GPIO_FUNC_I2C,
-					     GPIO_NO_PULL, GPIO_2MA, 1);
-		break;
-	case GSBI_ID_4:
-			/* Configure GPIOs 13 - SCL, 12 - SDA, 2mA gpio_en */
-			gpio_tlmm_config_set(12, GPIO_FUNC_I2C,
-					     GPIO_NO_PULL, GPIO_2MA, 1);
-			gpio_tlmm_config_set(13, GPIO_FUNC_I2C,
-					     GPIO_NO_PULL, GPIO_2MA, 1);
-		break;
-	case GSBI_ID_1:
-			/* Configure GPIOs 54 - SCL, 53 - SDA, 2mA gpio_en */
-			gpio_tlmm_config_set(54, GPIO_FUNC_I2C,
-					     GPIO_NO_PULL, GPIO_2MA, 1);
-			gpio_tlmm_config_set(53, GPIO_FUNC_I2C,
-					     GPIO_NO_PULL, GPIO_2MA, 1);
+	switch (id) {
+	case BLSP_QUP_ID_0:
+	case BLSP_QUP_ID_1:
+	case BLSP_QUP_ID_2:
+	case BLSP_QUP_ID_3:
+#if defined(IPQ40XX_I2C0_PINGROUP_1) || defined(IPQ40XX_I2C0_PINGROUP_2)
+		gpio_tlmm_config_set(SDA_GPIO, GPIO_FUNC_SDA,
+				     GPIO_NO_PULL, GPIO_2MA, 1);
+		gpio_tlmm_config_set(SCL_GPIO, GPIO_FUNC_SCL,
+				     GPIO_NO_PULL, GPIO_2MA, 1);
+#endif /* Pin Group 1 or 2 */
 		break;
 	default:
 		return 1;
diff --git a/src/mainboard/google/gale/chromeos.c b/src/mainboard/google/gale/chromeos.c
index c4af04853c..7430407c89 100644
--- a/src/mainboard/google/gale/chromeos.c
+++ b/src/mainboard/google/gale/chromeos.c
@@ -20,7 +20,7 @@
 #include <drivers/i2c/ww_ring/ww_ring.h>
 #include <gpio.h>
 #include <soc/cdp.h>
-#include <soc/gsbi.h>
+#include <soc/blsp.h>
 #include <string.h>
 #include <timer.h>
 #include <vendorcode/google/chromeos/chromeos.h>
diff --git a/src/mainboard/google/gale/mainboard.c b/src/mainboard/google/gale/mainboard.c
index a8117af1e3..e1a23c937f 100644
--- a/src/mainboard/google/gale/mainboard.c
+++ b/src/mainboard/google/gale/mainboard.c
@@ -22,6 +22,7 @@
 #include <soc/clock.h>
 #include <soc/soc_services.h>
 #include <soc/usb.h>
+#include <soc/blsp.h>
 #include <symbols.h>
 
 #include <vendorcode/google/chromeos/chromeos.h>
@@ -37,7 +38,7 @@ static void setup_usb(void)
 }
 
 #define TPM_RESET_GPIO		19
-static void ipq_setup_tpm(void)
+void ipq_setup_tpm(void)
 {
 #ifdef CONFIG_I2C_TPM
 	gpio_tlmm_config_set(TPM_RESET_GPIO, FUNC_SEL_GPIO,