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| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2019-08-26 13:59:54 +0300 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2019-08-27 11:52:13 +0000 |
| commit | 2a3f9f543a04a6382c40bc9b4f6a3b5c4846a4f2 (patch) | |
| tree | 701127d5ee343e799a88b7b3b6cbdfb4ecf95c44 /src/mainboard | |
| parent | eb6cac2f16b2df0922d5104481d36029d4a13712 (diff) | |
| download | coreboot-2a3f9f543a04a6382c40bc9b4f6a3b5c4846a4f2.tar.xz | |
smsc/superio/sio1007: Fix header name
The file chip.h has a special purpose for defining the
configuration structure used in static devicetree.
Change-Id: If0289c29ca72768009c1b7166311bc4c3cee4171
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35095
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Diffstat (limited to 'src/mainboard')
| -rw-r--r-- | src/mainboard/compulab/intense_pc/romstage.c | 2 | ||||
| -rw-r--r-- | src/mainboard/intel/emeraldlake2/romstage.c | 2 |
2 files changed, 2 insertions, 2 deletions
diff --git a/src/mainboard/compulab/intense_pc/romstage.c b/src/mainboard/compulab/intense_pc/romstage.c index 6c3d980b65..74f00c21d1 100644 --- a/src/mainboard/compulab/intense_pc/romstage.c +++ b/src/mainboard/compulab/intense_pc/romstage.c @@ -17,7 +17,7 @@ #include <arch/io.h> #include <device/pci_ops.h> #include <northbridge/intel/sandybridge/raminit_native.h> -#include <superio/smsc/sio1007/chip.h> +#include <superio/smsc/sio1007/sio1007.h> #include <southbridge/intel/bd82x6x/pch.h> #define SIO_PORT 0x164e diff --git a/src/mainboard/intel/emeraldlake2/romstage.c b/src/mainboard/intel/emeraldlake2/romstage.c index a28ae78f28..ee3cec1ebf 100644 --- a/src/mainboard/intel/emeraldlake2/romstage.c +++ b/src/mainboard/intel/emeraldlake2/romstage.c @@ -19,7 +19,7 @@ #include <device/pci_ops.h> #include <device/pci_def.h> #include <cpu/x86/lapic.h> -#include <superio/smsc/sio1007/chip.h> +#include <superio/smsc/sio1007/sio1007.h> #include <northbridge/intel/sandybridge/sandybridge.h> #include <northbridge/intel/sandybridge/raminit.h> #include <northbridge/intel/sandybridge/raminit_native.h> |