diff options
author | Julius Werner <jwerner@chromium.org> | 2018-06-26 12:36:24 -0700 |
---|---|---|
committer | Julius Werner <jwerner@chromium.org> | 2018-08-02 22:09:07 +0000 |
commit | 302e7bc5de78a073fa14f31a655fa6fce803e1e3 (patch) | |
tree | 74f6024998d2bbcab0c4ffc66fd464dd88aef76a /src/mainboard | |
parent | cc7a411fc5a4e62c9211b882095ddde98640d63b (diff) | |
download | coreboot-302e7bc5de78a073fa14f31a655fa6fce803e1e3.tar.xz |
cheza: Add board ID, RAM code and SKU ID
This patch adds the required callbacks to read all strapping IDs on
Cheza.
Change-Id: I6437bbd03bdd00dfeedcafebabeb00b13588d052
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/27789
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Diffstat (limited to 'src/mainboard')
-rw-r--r-- | src/mainboard/google/cheza/Makefile.inc | 18 | ||||
-rw-r--r-- | src/mainboard/google/cheza/boardid.c | 50 |
2 files changed, 68 insertions, 0 deletions
diff --git a/src/mainboard/google/cheza/Makefile.inc b/src/mainboard/google/cheza/Makefile.inc index 0e2f6bddb0..04099e2033 100644 --- a/src/mainboard/google/cheza/Makefile.inc +++ b/src/mainboard/google/cheza/Makefile.inc @@ -1,15 +1,33 @@ +## +## This file is part of the coreboot project. +## +## Copyright 2018 Google LLC +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +bootblock-y += boardid.c bootblock-y += memlayout.ld bootblock-y += chromeos.c bootblock-y += bootblock.c +verstage-y += boardid.c verstage-y += memlayout.ld verstage-y += chromeos.c +romstage-y += boardid.c romstage-y += memlayout.ld romstage-y += chromeos.c romstage-y += romstage.c +ramstage-y += boardid.c ramstage-y += memlayout.ld ramstage-y += chromeos.c ramstage-y += mainboard.c diff --git a/src/mainboard/google/cheza/boardid.c b/src/mainboard/google/cheza/boardid.c new file mode 100644 index 0000000000..fffac82ab6 --- /dev/null +++ b/src/mainboard/google/cheza/boardid.c @@ -0,0 +1,50 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <boardid.h> +#include <gpio.h> + +uint32_t board_id(void) +{ + const gpio_t pins[] = {[2] = GPIO(51), [1] = GPIO(62), [0] = GPIO(38)}; + static uint32_t id = UNDEFINED_STRAPPING_ID; + + if (id == UNDEFINED_STRAPPING_ID) + id = gpio_base2_value(pins, ARRAY_SIZE(pins)); + + return id; +} + +uint32_t ram_code(void) +{ + const gpio_t pins[] = {[1] = GPIO(147), [0] = GPIO(146)}; + static uint32_t id = UNDEFINED_STRAPPING_ID; + + if (id == UNDEFINED_STRAPPING_ID) + id = gpio_base2_value(pins, ARRAY_SIZE(pins)); + + return id; +} + +uint32_t sku_id(void) +{ + const gpio_t pins[] = {[1] = GPIO(113), [0] = GPIO(79)}; + static uint32_t id = UNDEFINED_STRAPPING_ID; + + if (id == UNDEFINED_STRAPPING_ID) + id = gpio_base2_value(pins, ARRAY_SIZE(pins)); + + return id; +} |