diff options
| author | Justin TerAvest <teravest@chromium.org> | 2018-02-20 14:24:36 -0700 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2018-02-22 16:27:36 +0000 |
| commit | 36b568ce7c7fa7bfc32382fb968a72cf02313404 (patch) | |
| tree | 1e63b278aa263790bc5c5eea1001654f47a49dce /src/mainboard | |
| parent | 2e81f394cffc6f1993a5f004356ed35f6064fe48 (diff) | |
| download | coreboot-36b568ce7c7fa7bfc32382fb968a72cf02313404.tar.xz | |
mb/google/kahlee: Correct bad gpio entry
There's no need to set the output enable here; this is already handled
by the native function. I'm making this correction in this change to
prevent the GPIO pin descriptions from getting confusing.
BUG=b:72875858
TEST=Booted, confirmed S5_MUX_CTRL high with and without this change.
Change-Id: I9e047be7169586c59892ef2bdab915683feeebda
Signed-off-by: Justin TerAvest <teravest@chromium.org>
Reviewed-on: https://review.coreboot.org/23829
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/mainboard')
| -rw-r--r-- | src/mainboard/google/kahlee/variants/baseboard/gpio.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/mainboard/google/kahlee/variants/baseboard/gpio.c b/src/mainboard/google/kahlee/variants/baseboard/gpio.c index 1e1f34b005..fb7ae96d13 100644 --- a/src/mainboard/google/kahlee/variants/baseboard/gpio.c +++ b/src/mainboard/google/kahlee/variants/baseboard/gpio.c @@ -91,7 +91,7 @@ const static struct soc_amd_stoneyridge_gpio gpio_set_stage_reset[] = { { GPIO_40, Function0, OUTPUT_H }, /* GPIO_42 - S5_MUX_CTRL */ - { GPIO_42, Function0, OUTPUT_H }, + { GPIO_42, Function0, INPUT }, /* GPIO_70 - WLAN_PE_RST_L */ { GPIO_70, Function0, OUTPUT_H }, |