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authorKane Chen <kane.chen@intel.com>2014-08-27 15:21:32 -0700
committerMarc Jones <marc.jones@se-eng.com>2015-03-27 06:30:04 +0100
commit4fef5a294b9024c54851756a813bffd65e7e1e32 (patch)
treed7b9799188c36b355fdb0fc56f3b0a1ab0fefa63 /src/mainboard
parenta7d8ea84c63e9c8103a6a8bc45b3aa92658a028f (diff)
downloadcoreboot-4fef5a294b9024c54851756a813bffd65e7e1e32.tar.xz
broadwell: Apply pcie updates from 2.1.0 ref code
some clock gating and pcie settings are missed in original code BUG=chrome-os-partner:28234 BRANCH=None TEST=build and boot on samus verify registers between samus and crb Original-Change-Id: I931276adb2f2667c4f9e7611acfd709b7232d492 Original-Signed-off-by: Kane Chen <kane.chen@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/214568 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> (cherry picked from commit 57e42c781d435092a08238461f0605dbf092e576) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Ia62a50f28a411bbd2ba51b94de17ca70051ea093 Reviewed-on: http://review.coreboot.org/8967 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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