diff options
| author | Julius Werner <jwerner@chromium.org> | 2014-11-10 19:53:45 -0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2015-04-10 20:50:29 +0200 |
| commit | 63451c73bd8fc587247b2e75587b1137fdbebf38 (patch) | |
| tree | 0608f1b055b9ed922ad6a2ba044895222bd88d9b /src/mainboard | |
| parent | 539e856643f9a7396638c05db5c4dbfb136e292b (diff) | |
| download | coreboot-63451c73bd8fc587247b2e75587b1137fdbebf38.tar.xz | |
veyron_jerry: Port CPU overshoot prevention
This patch ports commit 567f616f (rk3288: slowly raise to max cpu
voltage to prevent overshoot) to Veyron_Jerry. It also fixes include
ordering and some comment grammar in the affected code.
BRANCH=None
BUG=chrome-os-partner:32716
TEST=None
Change-Id: I4ac14a38e4b3acc4926d4f51f409ff12d9c841cf
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 679014bc843788e8d4d5f5c7470ae76f8be5e942
Original-Change-Id: I9c0aba40ddd8a0852391df184034baa740d063df
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/228938
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/9550
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/mainboard')
| -rw-r--r-- | src/mainboard/google/veyron_jerry/bootblock.c | 10 | ||||
| -rw-r--r-- | src/mainboard/google/veyron_pinky/bootblock.c | 7 |
2 files changed, 10 insertions, 7 deletions
diff --git a/src/mainboard/google/veyron_jerry/bootblock.c b/src/mainboard/google/veyron_jerry/bootblock.c index b34199dfe5..30b00e1145 100644 --- a/src/mainboard/google/veyron_jerry/bootblock.c +++ b/src/mainboard/google/veyron_jerry/bootblock.c @@ -20,6 +20,7 @@ #include <arch/io.h> #include <bootblock_common.h> +#include <delay.h> #include <soc/clock.h> #include <soc/i2c.h> #include <soc/grf.h> @@ -32,11 +33,16 @@ void bootblock_mainboard_init(void) { - /* cpu frequency will up to 1.8GHz, so the buck1 must up to 1.3v */ + /* Up VDD_CPU (BUCK1) to 1.4V to support max CPU frequency (1.8GHz). */ setbits_le32(&rk3288_pmu->iomux_i2c0scl, IOMUX_I2C0SCL); setbits_le32(&rk3288_pmu->iomux_i2c0sda, IOMUX_I2C0SDA); i2c_init(PMIC_BUS, 400*KHz); - rk808_configure_buck(PMIC_BUS, 1, 1300); + + /* Slowly raise to max CPU voltage to prevent overshoot */ + rk808_configure_buck(PMIC_BUS, 1, 1200); + udelay(175);/* Must wait for voltage to stabilize,2mV/us */ + rk808_configure_buck(PMIC_BUS, 1, 1400); + udelay(100);/* Must wait for voltage to stabilize,2mV/us */ rkclk_configure_cpu(); /* i2c1 for tpm */ diff --git a/src/mainboard/google/veyron_pinky/bootblock.c b/src/mainboard/google/veyron_pinky/bootblock.c index 99719c4024..30b00e1145 100644 --- a/src/mainboard/google/veyron_pinky/bootblock.c +++ b/src/mainboard/google/veyron_pinky/bootblock.c @@ -20,6 +20,7 @@ #include <arch/io.h> #include <bootblock_common.h> +#include <delay.h> #include <soc/clock.h> #include <soc/i2c.h> #include <soc/grf.h> @@ -27,16 +28,12 @@ #include <soc/rk808.h> #include <soc/spi.h> #include <vendorcode/google/chromeos/chromeos.h> -#include <delay.h> #include "board.h" void bootblock_mainboard_init(void) { - /* cpu frequency will up to 1.8GHz, - * in our experience the buck1 - * must up to 1.4v - */ + /* Up VDD_CPU (BUCK1) to 1.4V to support max CPU frequency (1.8GHz). */ setbits_le32(&rk3288_pmu->iomux_i2c0scl, IOMUX_I2C0SCL); setbits_le32(&rk3288_pmu->iomux_i2c0sda, IOMUX_I2C0SDA); i2c_init(PMIC_BUS, 400*KHz); |