diff options
| author | Shelley Chen <shchen@google.com> | 2019-01-29 15:30:14 -0800 |
|---|---|---|
| committer | Shelley Chen <shchen@google.com> | 2019-02-01 18:34:57 +0000 |
| commit | 757571eec16295d66a8c06033a61b73bad9c06fa (patch) | |
| tree | f6c3c85c529f964a634d5056ed2f4d205e43cd77 /src/mainboard | |
| parent | fb7a1a420c4abf6a385b865185a11db4e6fdf284 (diff) | |
| download | coreboot-757571eec16295d66a8c06033a61b73bad9c06fa.tar.xz | |
mb/google/hatch: Enable S0ix
BUG=b:123540469
BRANCH=None
TEST=None
Change-Id: I713e6ad70efdd152895afa45aee44a5b53a8136b
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/31157
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard')
| -rw-r--r-- | src/mainboard/google/hatch/variants/baseboard/devicetree.cb | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb index cea64e4237..2bc4f785a8 100644 --- a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb @@ -55,6 +55,8 @@ chip soc/intel/cannonlake register "HeciEnabled" = "1" # Enable Speed Shift Technology support register "speed_shift_enable" = "1" + # Enable S0ix + register "s0ix_enable" = "1" register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC2)" # Type-C Port 0 register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC2)" # Type-C Port 1 |