diff options
| author | Furquan Shaikh <furquan@chromium.org> | 2017-12-04 12:17:24 -0800 |
|---|---|---|
| committer | Furquan Shaikh <furquan@google.com> | 2017-12-06 18:23:55 +0000 |
| commit | 763b406107772ba57cf819fb12b9f3b78b9bf593 (patch) | |
| tree | 77ad534721f169ee9b34a9de5f9d52a2ad8d1409 /src/mainboard | |
| parent | bea9b473d12f4c802eec78ef9cf7c5f5004e696a (diff) | |
| download | coreboot-763b406107772ba57cf819fb12b9f3b78b9bf593.tar.xz | |
mb/google/poppy/variants/soraka: Disable SPI TPM
Soraka is no longer using SPI TPM. This change disables GSPI0 in
device tree and updates gpio config accordingly.
Change-Id: Ia0554ce3a0d553631123cc2b23b6dc2f6f40a1a3
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/22699
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/mainboard')
| -rw-r--r-- | src/mainboard/google/poppy/variants/soraka/devicetree.cb | 18 | ||||
| -rw-r--r-- | src/mainboard/google/poppy/variants/soraka/gpio.c | 31 |
2 files changed, 2 insertions, 47 deletions
diff --git a/src/mainboard/google/poppy/variants/soraka/devicetree.cb b/src/mainboard/google/poppy/variants/soraka/devicetree.cb index 5e5a53730d..f71a1eb1d3 100644 --- a/src/mainboard/google/poppy/variants/soraka/devicetree.cb +++ b/src/mainboard/google/poppy/variants/soraka/devicetree.cb @@ -232,13 +232,6 @@ chip soc/intel/skylake }, }" - # Use GSPI0 for cr50 TPM. Early init is required to set up a BAR for TPM - # communication before memory is up. - register "gspi[0]" = "{ - .speed_mhz = 1, - .early_init = 1, - }" - # Must leave UART0 enabled or SD/eMMC will not work as PCI register "SerialIoDevMode" = "{ [PchSerialIoIndexI2C0] = PchSerialIoPci, @@ -247,7 +240,7 @@ chip soc/intel/skylake [PchSerialIoIndexI2C3] = PchSerialIoDisabled, [PchSerialIoIndexI2C4] = PchSerialIoPci, [PchSerialIoIndexI2C5] = PchSerialIoPci, - [PchSerialIoIndexSpi0] = PchSerialIoPci, + [PchSerialIoIndexSpi0] = PchSerialIoDisabled, [PchSerialIoIndexSpi1] = PchSerialIoDisabled, [PchSerialIoIndexUart0] = PchSerialIoPci, [PchSerialIoIndexUart1] = PchSerialIoDisabled, @@ -358,14 +351,7 @@ chip soc/intel/skylake device pci 1d.3 off end # PCI Express Port 12 device pci 1e.0 on end # UART #0 device pci 1e.1 off end # UART #1 - device pci 1e.2 on - chip drivers/spi/acpi - register "hid" = "ACPI_DT_NAMESPACE_HID" - register "compat_string" = ""google,cr50"" - register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_E0_IRQ)" - device spi 0 on end - end - end # GSPI #0 + device pci 1e.2 off end # GSPI #0 device pci 1e.3 off end # GSPI #1 device pci 1e.4 on end # eMMC device pci 1e.5 off end # SDIO diff --git a/src/mainboard/google/poppy/variants/soraka/gpio.c b/src/mainboard/google/poppy/variants/soraka/gpio.c index d861e59368..e0a6b04c48 100644 --- a/src/mainboard/google/poppy/variants/soraka/gpio.c +++ b/src/mainboard/google/poppy/variants/soraka/gpio.c @@ -92,16 +92,6 @@ static const struct pad_config gpio_table[] = { PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), /* B14 : SPKR ==> NC */ PAD_CFG_NC(GPP_B14), -#if IS_ENABLED(CONFIG_POPPY_USE_SPI_TPM) - /* B15 : GSPI0_CS# ==> PCH_SPI_H1_3V3_CS_L */ - PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1), - /* B16 : GSPI0_CLK ==> PCH_SPI_H1_3V3_CLK */ - PAD_CFG_NF(GPP_B16, NONE, DEEP, NF1), - /* B17 : GSPI0_MISO ==> PCH_SPI_H1_3V3_MISO */ - PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1), - /* B18 : GSPI0_MOSI ==> PCH_SPI_H1_3V3_MOSI */ - PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1), -#else /* B15 : GSPI0_CS# ==> NC */ PAD_CFG_NC(GPP_B15), /* B16 : GSPI0_CLK ==> NC */ @@ -110,7 +100,6 @@ static const struct pad_config gpio_table[] = { PAD_CFG_NC(GPP_B17), /* B18 : GSPI0_MOSI ==> NC */ PAD_CFG_NC(GPP_B18), -#endif /* B19 : GSPI1_CS# ==> NC */ PAD_CFG_NC(GPP_B19), /* B20 : GSPI1_CLK ==> NC */ @@ -158,17 +147,10 @@ static const struct pad_config gpio_table[] = { PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), /* C17 : I2C0_SCL ==> PCH_I2C0_TOUCHSCREEN_3V3_SCL */ PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), -#if IS_ENABLED(CONFIG_POPPY_USE_I2C_TPM) /* C18 : I2C1_SDA ==> PCH_I2C1_H1_3V3_SDA */ PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1), /* C19 : I2C1_SCL ==> PCH_I2C1_H1_3V3_SCL */ PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1), -#else - /* C18 : I2C1_SDA ==> NC */ - PAD_CFG_NC(GPP_C18), - /* C19 : I2C1_SCL ==> NC */ - PAD_CFG_NC(GPP_C19), -#endif /* C20 : UART2_RXD ==> PCHRX_SERVOTX_UART */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* C21 : UART2_TXD ==> PCHTX_SERVORX_UART */ @@ -373,23 +355,10 @@ static const struct pad_config gpio_table[] = { static const struct pad_config early_gpio_table[] = { /* B8 : SRCCLKREQ3# ==> WLAN_PE_RST */ PAD_CFG_GPO(GPP_B8, 0, RSMRST), -#if IS_ENABLED(CONFIG_POPPY_USE_SPI_TPM) - /* B15 : GSPI0_CS# ==> PCH_SPI_H1_3V3_CS_L */ - PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1), - /* B16 : GSPI0_CLK ==> PCH_SPI_H1_3V3_CLK */ - PAD_CFG_NF(GPP_B16, NONE, DEEP, NF1), - /* B17 : GSPI0_MISO ==> PCH_SPI_H1_3V3_MISO */ - PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1), - /* B18 : GSPI0_MOSI ==> PCH_SPI_H1_3V3_MOSI */ - PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1), -#endif - -#if IS_ENABLED(CONFIG_POPPY_USE_I2C_TPM) /* C18 : I2C1_SDA ==> PCH_I2C1_H1_3V3_SDA */ PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1), /* C19 : I2C1_SCL ==> PCH_I2C1_H1_3V3_SCL */ PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1), -#endif /* Ensure UART pins are in native mode for H1. */ /* C20 : UART2_RXD ==> PCHRX_SERVOTX_UART */ |