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authorDuncan Laurie <dlaurie@chromium.org>2013-03-08 16:34:33 -0800
committerRonald G. Minnich <rminnich@gmail.com>2013-03-21 23:09:49 +0100
commit7922b468b51eea58c7238f11b21820b8d3747d6b (patch)
treea3675447a57e122c3987beb4c513f0c11876268e /src/mainboard
parentf5966b14e8d2a0613d5cbafbf73d76bed371899d (diff)
downloadcoreboot-7922b468b51eea58c7238f11b21820b8d3747d6b.tar.xz
lynxpoint: Fix GPIO and PM base reservations
The kernel ACPI was not happy with the Add inside a ResourceTemplate (or perhaps within the IO declaration) Instead make a buffer of IO reservations and turn _CRS into a method that updates the buffer depending on the chipset type. This adds an \ISLP() method that checks the chipset LPC device ID to see if it is -LP or -H. It also increases the PM base reservation to 256 bytes and moves both GPIO and PM base to above 0x1000 on -LP chipsets. Change-Id: I747b658588a4d8ed15a0134009a7c0d74b3916ba Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/2815 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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