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authorDavid Hendricks <dhendrix@chromium.org>2013-01-10 11:44:58 -0800
committerRonald G. Minnich <rminnich@gmail.com>2013-01-10 23:13:39 +0100
commit8a5ee9ce04cb88a57cf0a0d8a405c9865c99c01a (patch)
tree13b7ddca4e5a691cdf1b2910e29e9de5ce48c945 /src/mainboard
parentd6b0889febfce600fe56fa2fe4785a19fb84174a (diff)
downloadcoreboot-8a5ee9ce04cb88a57cf0a0d8a405c9865c99c01a.tar.xz
armv7: replace magic constant for romstage location
This replaces 0x02023400 with an SoC-specific Kconfig variable. Change-Id: I21482d54a1e1fa6c4437c030ddae2b0bb3331551 Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/2130 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'src/mainboard')
-rw-r--r--src/mainboard/google/snow/Kconfig4
1 files changed, 4 insertions, 0 deletions
diff --git a/src/mainboard/google/snow/Kconfig b/src/mainboard/google/snow/Kconfig
index 4a7fced3c0..21cdfa5fd2 100644
--- a/src/mainboard/google/snow/Kconfig
+++ b/src/mainboard/google/snow/Kconfig
@@ -63,6 +63,10 @@ config SPL_TEXT_BASE
help
Location of SPL. Default location is within iRAM region.
+config ROMSTAGE_BASE
+ hex
+ default SPL_TEXT_BASE
+
# FIXME: increased "SPL" size to get around build issues
#config SPL_MAX_SIZE
# hex "SPL executable max size"