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| author | Frans Hendriks <fhendriks@eltan.com> | 2019-12-09 10:02:26 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-12-11 11:35:21 +0000 |
| commit | 8d98d80e5330f465c315a7aade4b754b8c6c79b3 (patch) | |
| tree | f90210ac0f89dae68fb31807c53a22df5029de7f /src/mainboard | |
| parent | 9484792ad1470117aeb9bd234adc86f7e9087b0b (diff) | |
| download | coreboot-8d98d80e5330f465c315a7aade4b754b8c6c79b3.tar.xz | |
mb/portwell/m107/devicetree.cb: Use IGD_MEMSIZE_32MB
Make code more readable.
Replace 1 by IGD_MEMSIZE_32MB for PcdIgdDvmtS0PreAlloc.
BUG=N/A
TEST=build
Change-Id: I5d84e575935e9e60610e1805e1402f290672b114
Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37616
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Diffstat (limited to 'src/mainboard')
| -rw-r--r-- | src/mainboard/portwell/m107/devicetree.cb | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/mainboard/portwell/m107/devicetree.cb b/src/mainboard/portwell/m107/devicetree.cb index 9a27fed8cf..f68b071a12 100644 --- a/src/mainboard/portwell/m107/devicetree.cb +++ b/src/mainboard/portwell/m107/devicetree.cb @@ -9,7 +9,7 @@ chip soc/intel/braswell register "PcdMrcInitMmioSize" = "0x0800" register "PcdMrcInitSpdAddr1" = "0xa0" register "PcdMrcInitSpdAddr2" = "0xa2" - register "PcdIgdDvmt50PreAlloc" = "1" + register "PcdIgdDvmt50PreAlloc" = "IGD_MEMSIZE_32MB" register "PcdApertureSize" = "2" register "PcdGttSize" = "1" register "PcdDvfsEnable" = "0" |