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| author | Furquan Shaikh <furquan@google.com> | 2020-05-15 17:37:07 -0700 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-05-28 09:43:09 +0000 |
| commit | 918ee62977394e7a5b0b20554d9f9017cfe602c3 (patch) | |
| tree | 4ffaeb5c6450691a1629aa4124606ee496af014d /src/mainboard | |
| parent | 32f385ebfabe0b33c8c026c3972e4af880e39a5a (diff) | |
| download | coreboot-918ee62977394e7a5b0b20554d9f9017cfe602c3.tar.xz | |
Revert "Revert "mb/google/volteer: Enable PCIEXP_HOTPLUG for TCSS TBT/USB4 ports""
This reverts commit 1726fa1f0ce474cde32e8b32be34a212aff3ffba.
Reason for revert: Resource allocator is split into old(v3) and
new(v4). So, this change to enable hotplug resource allocator for
volteer can land back.
BUG=b:149186922
Change-Id: Ib6a4df610b045fbc885c70bff3698a032b79f770
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41468
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/mainboard')
| -rw-r--r-- | src/mainboard/google/volteer/Kconfig | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/src/mainboard/google/volteer/Kconfig b/src/mainboard/google/volteer/Kconfig index 9c7292f6d6..7ed685a8e5 100644 --- a/src/mainboard/google/volteer/Kconfig +++ b/src/mainboard/google/volteer/Kconfig @@ -19,6 +19,7 @@ config BOARD_GOOGLE_BASEBOARD_VOLTEER select MAINBOARD_HAS_CHROMEOS select MAINBOARD_HAS_SPI_TPM_CR50 select MAINBOARD_HAS_TPM2 + select PCIEXP_HOTPLUG select SOC_INTEL_TIGERLAKE if BOARD_GOOGLE_BASEBOARD_VOLTEER @@ -72,6 +73,20 @@ config MAX_CPUS int default 8 +# Reserving resources for PCIe Hotplug as per TGL BIOS Spec (doc #611569) +# Revision 0.7.6 Section 7.2.5.1.5 +config PCIEXP_HOTPLUG_BUSES + int + default 42 + +config PCIEXP_HOTPLUG_MEM + hex + default 0xc200000 # 194 MiB + +config PCIEXP_HOTPLUG_PREFETCH_MEM + hex + default 0x1c000000 # 448 MiB + config TPM_TIS_ACPI_INTERRUPT int default 21 # GPE0_DW0_21 (GPP_C21) |