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| author | Duncan Laurie <dlaurie@chromium.org> | 2013-05-01 11:12:53 -0700 |
|---|---|---|
| committer | Alexandru Gagniuc <mr.nuke.me@gmail.com> | 2013-11-24 06:17:31 +0100 |
| commit | a103d0715c178d9f68720dfc24d1ba880c39590c (patch) | |
| tree | 4ab792c715df5da6024642d9b7a1f1dea44ab2d6 /src/mainboard | |
| parent | e820a6ce833aacb0cf9500809b03493a01dcf9c0 (diff) | |
| download | coreboot-a103d0715c178d9f68720dfc24d1ba880c39590c.tar.xz | |
slippy: Prepare LPC IO decode ranges for EC
- 0x200-0x208 for host command window
- 0x800-0x8ff for host command arguments and parameters
- 0x900-0x9ff for exported EC memory map
Change-Id: I064b969843ef0d3c602793d1cb3d82715775c05e
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/49755
Reviewed-on: http://review.coreboot.org/4151
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Diffstat (limited to 'src/mainboard')
| -rw-r--r-- | src/mainboard/google/slippy/devicetree.cb | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/src/mainboard/google/slippy/devicetree.cb b/src/mainboard/google/slippy/devicetree.cb index 8cf387fff8..5fb3cb4c1b 100644 --- a/src/mainboard/google/slippy/devicetree.cb +++ b/src/mainboard/google/slippy/devicetree.cb @@ -41,6 +41,10 @@ chip northbridge/intel/haswell register "pirqg_routing" = "0x80" register "pirqh_routing" = "0x80" + # EC range is 0x800-0x9ff + register "gen1_dec" = "0x00fc0801" + register "gen2_dec" = "0x00fc0901" + register "alt_gp_smi_en" = "0x0000" register "gpe0_en_1" = "0x00000000" # EC_SCI is GPIO36 |