diff options
| author | Elyes HAOUAS <ehaouas@noos.fr> | 2018-06-09 11:59:00 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2018-06-14 09:32:34 +0000 |
| commit | b0f1988f893bf5f581917816b11e810309955143 (patch) | |
| tree | c4bcf6f1d9384b99cfcbfab4426de9f9f106e720 /src/mainboard | |
| parent | 68c851bcd702e7816cdb6e504f7386ec404ecf13 (diff) | |
| download | coreboot-b0f1988f893bf5f581917816b11e810309955143.tar.xz | |
src: Get rid of unneeded whitespace
Change-Id: I630d49ab504d9f6e052806b516a600fa41b9a8da
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26991
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/mainboard')
65 files changed, 1011 insertions, 1015 deletions
diff --git a/src/mainboard/advansus/a785e-i/devicetree.cb b/src/mainboard/advansus/a785e-i/devicetree.cb index 5e7280a3cb..c78c508474 100644 --- a/src/mainboard/advansus/a785e-i/devicetree.cb +++ b/src/mainboard/advansus/a785e-i/devicetree.cb @@ -2,7 +2,7 @@ chip northbridge/amd/amdfam10/root_complex device cpu_cluster 0 on chip cpu/amd/socket_ASB2 #L1 and DDR3 - device lapic 0 on end + device lapic 0 on end end end device domain 0 on @@ -54,49 +54,49 @@ chip northbridge/amd/amdfam10/root_complex device i2c 53 on end end end # SM - device pci 14.1 on end # IDE 0x439c - device pci 14.2 on end # HDA 0x4383 + device pci 14.1 on end # IDE 0x439c + device pci 14.2 on end # HDA 0x4383 device pci 14.3 on - chip superio/winbond/w83627hf - device pnp 2e.0 off # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 2e.1 off # Parallel Port - io 0x60 = 0x378 - irq 0x70 = 7 - end - device pnp 2e.2 on # Com1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.3 on # Com2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.5 on # Keyboard - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - irq 0x72 = 12 - end - device pnp 2e.6 off # SFI - io 0x62 = 0x100 - end - device pnp 2e.7 off # GPIO_GAME_MIDI - io 0x60 = 0x220 - io 0x62 = 0x300 - irq 0x70 = 9 - end - device pnp 2e.8 off end # WDTO_PLED - device pnp 2e.9 off end # GPIO_SUSLED - device pnp 2e.a off end # ACPI - device pnp 2e.b on # HW Monitor - io 0x60 = 0x290 - irq 0x70 = 5 - end - end #superio/winbond/w83627hf + chip superio/winbond/w83627hf + device pnp 2e.0 off # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 2e.1 off # Parallel Port + io 0x60 = 0x378 + irq 0x70 = 7 + end + device pnp 2e.2 on # Com1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.3 on # Com2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.5 on # Keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + irq 0x72 = 12 + end + device pnp 2e.6 off # SFI + io 0x62 = 0x100 + end + device pnp 2e.7 off # GPIO_GAME_MIDI + io 0x60 = 0x220 + io 0x62 = 0x300 + irq 0x70 = 9 + end + device pnp 2e.8 off end # WDTO_PLED + device pnp 2e.9 off end # GPIO_SUSLED + device pnp 2e.a off end # ACPI + device pnp 2e.b on # HW Monitor + io 0x60 = 0x290 + irq 0x70 = 5 + end + end #superio/winbond/w83627hf end # LPC 0x439d device pci 14.4 off end # PCIB 0x4384, NOTE: PCI interface pins shared with GPIO {GPIO 35:0} device pci 14.5 on end # USB 2 diff --git a/src/mainboard/amd/bettong/acpi/gpe.asl b/src/mainboard/amd/bettong/acpi/gpe.asl index 9a8469832b..87b0d2169d 100644 --- a/src/mainboard/amd/bettong/acpi/gpe.asl +++ b/src/mainboard/amd/bettong/acpi/gpe.asl @@ -71,4 +71,4 @@ Scope(\_GPE) { /* Start Scope GPE */ Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ } -} /* End Scope GPE */ +} /* End Scope GPE */ diff --git a/src/mainboard/amd/bettong/dsdt.asl b/src/mainboard/amd/bettong/dsdt.asl index 37257c42ff..505b519776 100644 --- a/src/mainboard/amd/bettong/dsdt.asl +++ b/src/mainboard/amd/bettong/dsdt.asl @@ -45,7 +45,7 @@ DefinitionBlock ( /* System Bus */ Scope(\_SB) { /* Start \_SB scope */ - /* global utility methods expected within the \_SB scope */ + /* global utility methods expected within the \_SB scope */ #include <arch/x86/acpi/globutil.asl> /* Describe IRQ Routing mapping for this platform (within the \_SB scope) */ diff --git a/src/mainboard/amd/bimini_fam10/devicetree.cb b/src/mainboard/amd/bimini_fam10/devicetree.cb index 0bcc9c16af..ba6a0fafcf 100644 --- a/src/mainboard/amd/bimini_fam10/devicetree.cb +++ b/src/mainboard/amd/bimini_fam10/devicetree.cb @@ -10,7 +10,7 @@ chip northbridge/amd/amdfam10/root_complex chip northbridge/amd/amdfam10 device pci 18.0 on # northbridge chip southbridge/amd/rs780 - device pci 0.0 on end # HT 0x9600 + device pci 0.0 on end # HT 0x9600 device pci 1.0 on end # Internal Graphics P2P bridge 0x9602 device pci 2.0 off end # PCIE P2P bridge (external graphics) 0x9603 device pci 3.0 off end # PCIE P2P bridge 0x960b @@ -38,7 +38,7 @@ chip northbridge/amd/amdfam10/root_complex device pci 12.2 on end # USB device pci 13.0 on end # USB device pci 13.2 on end # USB - device pci 14.0 on # SM + device pci 14.0 on # SM chip drivers/generic/generic #dimm 0-0-0 device i2c 50 on end end diff --git a/src/mainboard/amd/bimini_fam10/dsdt.asl b/src/mainboard/amd/bimini_fam10/dsdt.asl index b6a8e17a42..96dc819045 100644 --- a/src/mainboard/amd/bimini_fam10/dsdt.asl +++ b/src/mainboard/amd/bimini_fam10/dsdt.asl @@ -234,9 +234,9 @@ DefinitionBlock ( PWMK, 1, PWNS, 1, - /* Offset(0x61), */ /* Options_1 */ - /* ,7, */ - /* R617,1, */ + /* Offset(0x61), */ /* Options_1 */ + /* ,7, */ + /* R617,1, */ Offset(0x65), /* UsbPMControl */ , 4, @@ -832,7 +832,7 @@ DefinitionBlock ( /* On older chips, clear PciExpWakeDisEn */ /*if (LLessEqual(\_SB.SBRI, 0x13)) { - * Store(0,\_SB.PWDE) + * Store(0,\_SB.PWDE) *} */ @@ -847,13 +847,13 @@ DefinitionBlock ( * used, so it could be removed. * * - * \_GTS OEM Going To Sleep method + * \_GTS OEM Going To Sleep method * - * Entry: - * Arg0=The value of the sleeping state S1=1, S2=2 + * Entry: + * Arg0=The value of the sleeping state S1=1, S2=2 * - * Exit: - * -none- + * Exit: + * -none- * * Method(\_GTS, 1) { * DBGO("\\_GTS\n") @@ -1020,7 +1020,7 @@ DefinitionBlock ( /* PCIe HotPlug event */ /* Method(_L0F) { - * DBGO("\\_GPE\\_L0F\n") + * DBGO("\\_GPE\\_L0F\n") * } */ @@ -1043,19 +1043,19 @@ DefinitionBlock ( /* GPM0 SCI event - Moved to USB.asl */ /* Method(_L13) { - * DBGO("\\_GPE\\_L13\n") + * DBGO("\\_GPE\\_L13\n") * } */ /* GPM1 SCI event - Moved to USB.asl */ /* Method(_L14) { - * DBGO("\\_GPE\\_L14\n") + * DBGO("\\_GPE\\_L14\n") * } */ /* GPM2 SCI event - Moved to USB.asl */ /* Method(_L15) { - * DBGO("\\_GPE\\_L15\n") + * DBGO("\\_GPE\\_L15\n") * } */ @@ -1067,7 +1067,7 @@ DefinitionBlock ( /* GPM8 SCI event - Moved to USB.asl */ /* Method(_L17) { - * DBGO("\\_GPE\\_L17\n") + * DBGO("\\_GPE\\_L17\n") * } */ @@ -1084,7 +1084,7 @@ DefinitionBlock ( /* GPM4 SCI event - Moved to USB.asl */ /* Method(_L19) { - * DBGO("\\_GPE\\_L19\n") + * DBGO("\\_GPE\\_L19\n") * } */ @@ -1115,7 +1115,7 @@ DefinitionBlock ( /* GPIO2 or GPIO66 SCI event */ /* Method(_L1E) { - * DBGO("\\_GPE\\_L1E\n") + * DBGO("\\_GPE\\_L1E\n") * } */ @@ -1125,7 +1125,7 @@ DefinitionBlock ( * } */ - } /* End Scope GPE */ + } /* End Scope GPE */ #include "acpi/usb.asl" @@ -1477,7 +1477,7 @@ DefinitionBlock ( ) #if 0 Memory32Fixed(READWRITE, 0, 0xA0000, BSMM) - Memory32Fixed(READONLY, 0x000A0000, 0x00020000, VGAM) /* VGA memory space */ + Memory32Fixed(READONLY, 0x000A0000, 0x00020000, VGAM) /* VGA memory space */ Memory32Fixed(READONLY, 0x000C0000, 0x00020000, EMM1) /* Assume C0000-E0000 empty */ Memory32Fixed(READONLY, 0x000E0000, 0x00020000, RDBS) /* BIOS ROM area */ @@ -1607,7 +1607,7 @@ DefinitionBlock ( /* On older chips, clear PciExpWakeDisEn */ /*if (LLessEqual(\SBRI, 0x13)) { - * Store(0,\PWDE) + * Store(0,\PWDE) * } */ } /* End Method(_SB._INI) */ diff --git a/src/mainboard/amd/bimini_fam10/romstage.c b/src/mainboard/amd/bimini_fam10/romstage.c index 0c26416e75..d4397b2372 100644 --- a/src/mainboard/amd/bimini_fam10/romstage.c +++ b/src/mainboard/amd/bimini_fam10/romstage.c @@ -80,7 +80,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) /* enable port80 decoding and southbridge poweron init */ sb800_lpc_port80(); - inb(0x80); /* Wait sometime before post to port80, otherwise reset was needed. */ + inb(0x80); /* Wait sometime before post to port80, otherwise reset was needed. */ } post_code(0x30); diff --git a/src/mainboard/amd/db-ft3b-lc/acpi/gpe.asl b/src/mainboard/amd/db-ft3b-lc/acpi/gpe.asl index 9a8469832b..87b0d2169d 100644 --- a/src/mainboard/amd/db-ft3b-lc/acpi/gpe.asl +++ b/src/mainboard/amd/db-ft3b-lc/acpi/gpe.asl @@ -71,4 +71,4 @@ Scope(\_GPE) { /* Start Scope GPE */ Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ } -} /* End Scope GPE */ +} /* End Scope GPE */ diff --git a/src/mainboard/amd/db-ft3b-lc/dsdt.asl b/src/mainboard/amd/db-ft3b-lc/dsdt.asl index 03d46dcf76..549adc00ec 100644 --- a/src/mainboard/amd/db-ft3b-lc/dsdt.asl +++ b/src/mainboard/amd/db-ft3b-lc/dsdt.asl @@ -46,7 +46,7 @@ DefinitionBlock ( /* System Bus */ Scope(\_SB) { /* Start \_SB scope */ - /* global utility methods expected within the \_SB scope */ + /* global utility methods expected within the \_SB scope */ #include <arch/x86/acpi/globutil.asl> /* Describe IRQ Routing mapping for this platform (within the \_SB scope) */ diff --git a/src/mainboard/amd/gardenia/acpi/gpe.asl b/src/mainboard/amd/gardenia/acpi/gpe.asl index e713ad6688..6429bc604a 100644 --- a/src/mainboard/amd/gardenia/acpi/gpe.asl +++ b/src/mainboard/amd/gardenia/acpi/gpe.asl @@ -66,4 +66,4 @@ Scope(\_GPE) { /* Start Scope GPE */ Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ } -} /* End Scope GPE */ +} /* End Scope GPE */ diff --git a/src/mainboard/amd/inagua/acpi/gpe.asl b/src/mainboard/amd/inagua/acpi/gpe.asl index 2f22758712..30e6fdcb3c 100644 --- a/src/mainboard/amd/inagua/acpi/gpe.asl +++ b/src/mainboard/amd/inagua/acpi/gpe.asl @@ -72,7 +72,7 @@ Scope(\_GPE) { /* Start Scope GPE */ Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ } -} /* End Scope GPE */ +} /* End Scope GPE */ /* Contains the GPEs for USB overcurrent */ #include "usb_oc.asl" diff --git a/src/mainboard/amd/inagua/acpi/sleep.asl b/src/mainboard/amd/inagua/acpi/sleep.asl index 0069aa9db2..47de049dbc 100644 --- a/src/mainboard/amd/inagua/acpi/sleep.asl +++ b/src/mainboard/amd/inagua/acpi/sleep.asl @@ -49,7 +49,7 @@ Method(\_PTS, 1) { /* On older chips, clear PciExpWakeDisEn */ /*if (LLessEqual(\_SB.SBRI, 0x13)) { - * Store(0,\_SB.PWDE) + * Store(0,\_SB.PWDE) *} */ diff --git a/src/mainboard/amd/inagua/acpi/usb_oc.asl b/src/mainboard/amd/inagua/acpi/usb_oc.asl index 299d4aa55c..6e9c701a26 100644 --- a/src/mainboard/amd/inagua/acpi/usb_oc.asl +++ b/src/mainboard/amd/inagua/acpi/usb_oc.asl @@ -36,7 +36,7 @@ Name(UOM9, 6) Method(UCOC, 0) { Sleep(20) - Store(0x13,CMTI) + Store(0x13,CMTI) Store(0,GPSL) } diff --git a/src/mainboard/amd/lamar/acpi/gpe.asl b/src/mainboard/amd/lamar/acpi/gpe.asl index c5753eea51..297d9b47cb 100644 --- a/src/mainboard/amd/lamar/acpi/gpe.asl +++ b/src/mainboard/amd/lamar/acpi/gpe.asl @@ -70,4 +70,4 @@ Scope(\_GPE) { /* Start Scope GPE */ Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ } -} /* End Scope GPE */ +} /* End Scope GPE */ diff --git a/src/mainboard/amd/lamar/acpi/sleep.asl b/src/mainboard/amd/lamar/acpi/sleep.asl index 2d26a54f6c..f7edfb9119 100644 --- a/src/mainboard/amd/lamar/acpi/sleep.asl +++ b/src/mainboard/amd/lamar/acpi/sleep.asl @@ -44,7 +44,7 @@ Method(\_PTS, 1) { /* On older chips, clear PciExpWakeDisEn */ /*if (LLessEqual(\_SB.SBRI, 0x13)) { - * Store(0,\_SB.PWDE) + * Store(0,\_SB.PWDE) *} */ diff --git a/src/mainboard/amd/mahogany_fam10/devicetree.cb b/src/mainboard/amd/mahogany_fam10/devicetree.cb index 5000b0c27c..dba1470f33 100644 --- a/src/mainboard/amd/mahogany_fam10/devicetree.cb +++ b/src/mainboard/amd/mahogany_fam10/devicetree.cb @@ -10,7 +10,7 @@ chip northbridge/amd/amdfam10/root_complex chip northbridge/amd/amdfam10 device pci 18.0 on # northbridge chip southbridge/amd/rs780 - device pci 0.0 on end # HT 0x9600 + device pci 0.0 on end # HT 0x9600 device pci 1.0 on end # Internal Graphics P2P bridge 0x9602 device pci 2.0 on end # PCIE P2P bridge (external graphics) 0x9603 device pci 3.0 on end # PCIE P2P bridge 0x960b @@ -40,7 +40,7 @@ chip northbridge/amd/amdfam10/root_complex device pci 13.0 on end # USB device pci 13.1 on end # USB device pci 13.2 on end # USB - device pci 14.0 on # SM + device pci 14.0 on # SM chip drivers/generic/generic #dimm 0-0-0 device i2c 50 on end end diff --git a/src/mainboard/amd/mahogany_fam10/dsdt.asl b/src/mainboard/amd/mahogany_fam10/dsdt.asl index fe2c9869fe..57afc29547 100644 --- a/src/mainboard/amd/mahogany_fam10/dsdt.asl +++ b/src/mainboard/amd/mahogany_fam10/dsdt.asl @@ -239,9 +239,9 @@ DefinitionBlock ( PWMK, 1, PWNS, 1, - /* Offset(0x61), */ /* Options_1 */ - /* ,7, */ - /* R617,1, */ + /* Offset(0x61), */ /* Options_1 */ + /* ,7, */ + /* R617,1, */ Offset(0x65), /* UsbPMControl */ , 4, @@ -837,7 +837,7 @@ DefinitionBlock ( /* On older chips, clear PciExpWakeDisEn */ /*if (LLessEqual(\_SB.SBRI, 0x13)) { - * Store(0,\_SB.PWDE) + * Store(0,\_SB.PWDE) *} */ @@ -853,13 +853,13 @@ DefinitionBlock ( * used, so it could be removed. * * - * \_GTS OEM Going To Sleep method + * \_GTS OEM Going To Sleep method * - * Entry: - * Arg0=The value of the sleeping state S1=1, S2=2 + * Entry: + * Arg0=The value of the sleeping state S1=1, S2=2 * - * Exit: - * -none- + * Exit: + * -none- * * Method(\_GTS, 1) { * DBGO("\\_GTS\n") @@ -1026,7 +1026,7 @@ DefinitionBlock ( /* PCIe HotPlug event */ /* Method(_L0F) { - * DBGO("\\_GPE\\_L0F\n") + * DBGO("\\_GPE\\_L0F\n") * } */ @@ -1049,19 +1049,19 @@ DefinitionBlock ( /* GPM0 SCI event - Moved to USB.asl */ /* Method(_L13) { - * DBGO("\\_GPE\\_L13\n") + * DBGO("\\_GPE\\_L13\n") * } */ /* GPM1 SCI event - Moved to USB.asl */ /* Method(_L14) { - * DBGO("\\_GPE\\_L14\n") + * DBGO("\\_GPE\\_L14\n") * } */ /* GPM2 SCI event - Moved to USB.asl */ /* Method(_L15) { - * DBGO("\\_GPE\\_L15\n") + * DBGO("\\_GPE\\_L15\n") * } */ @@ -1073,7 +1073,7 @@ DefinitionBlock ( /* GPM8 SCI event - Moved to USB.asl */ /* Method(_L17) { - * DBGO("\\_GPE\\_L17\n") + * DBGO("\\_GPE\\_L17\n") * } */ @@ -1090,7 +1090,7 @@ DefinitionBlock ( /* GPM4 SCI event - Moved to USB.asl */ /* Method(_L19) { - * DBGO("\\_GPE\\_L19\n") + * DBGO("\\_GPE\\_L19\n") * } */ @@ -1121,7 +1121,7 @@ DefinitionBlock ( /* GPIO2 or GPIO66 SCI event */ /* Method(_L1E) { - * DBGO("\\_GPE\\_L1E\n") + * DBGO("\\_GPE\\_L1E\n") * } */ @@ -1131,7 +1131,7 @@ DefinitionBlock ( * } */ - } /* End Scope GPE */ + } /* End Scope GPE */ #include "acpi/usb.asl" @@ -1520,7 +1520,7 @@ DefinitionBlock ( 0xF300 /* length */ ) - Memory32Fixed(READONLY, 0x000A0000, 0x00020000, VGAM) /* VGA memory space */ + Memory32Fixed(READONLY, 0x000A0000, 0x00020000, VGAM) /* VGA memory space */ #if 0 Memory32Fixed(READWRITE, 0, 0xA0000, BSMM) Memory32Fixed(READONLY, 0x000C0000, 0x00020000, EMM1) /* Assume C0000-E0000 empty */ @@ -1652,7 +1652,7 @@ DefinitionBlock ( /* On older chips, clear PciExpWakeDisEn */ /*if (LLessEqual(\SBRI, 0x13)) { - * Store(0,\PWDE) + * Store(0,\PWDE) * } */ } /* End Method(_SB._INI) */ diff --git a/src/mainboard/amd/olivehill/acpi/gpe.asl b/src/mainboard/amd/olivehill/acpi/gpe.asl index 9a8469832b..87b0d2169d 100644 --- a/src/mainboard/amd/olivehill/acpi/gpe.asl +++ b/src/mainboard/amd/olivehill/acpi/gpe.asl @@ -71,4 +71,4 @@ Scope(\_GPE) { /* Start Scope GPE */ Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ } -} /* End Scope GPE */ +} /* End Scope GPE */ diff --git a/src/mainboard/amd/olivehill/dsdt.asl b/src/mainboard/amd/olivehill/dsdt.asl index e70998921c..e2d02087cc 100644 --- a/src/mainboard/amd/olivehill/dsdt.asl +++ b/src/mainboard/amd/olivehill/dsdt.asl @@ -46,7 +46,7 @@ DefinitionBlock ( /* System Bus */ Scope(\_SB) { /* Start \_SB scope */ - /* global utility methods expected within the \_SB scope */ + /* global utility methods expected within the \_SB scope */ #include <arch/x86/acpi/globutil.asl> /* Describe IRQ Routing mapping for this platform (within the \_SB scope) */ diff --git a/src/mainboard/amd/olivehillplus/acpi/gpe.asl b/src/mainboard/amd/olivehillplus/acpi/gpe.asl index 9a8469832b..87b0d2169d 100644 --- a/src/mainboard/amd/olivehillplus/acpi/gpe.asl +++ b/src/mainboard/amd/olivehillplus/acpi/gpe.asl @@ -71,4 +71,4 @@ Scope(\_GPE) { /* Start Scope GPE */ Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ } -} /* End Scope GPE */ +} /* End Scope GPE */ diff --git a/src/mainboard/amd/olivehillplus/dsdt.asl b/src/mainboard/amd/olivehillplus/dsdt.asl index 03d46dcf76..549adc00ec 100644 --- a/src/mainboard/amd/olivehillplus/dsdt.asl +++ b/src/mainboard/amd/olivehillplus/dsdt.asl @@ -46,7 +46,7 @@ DefinitionBlock ( /* System Bus */ Scope(\_SB) { /* Start \_SB scope */ - /* global utility methods expected within the \_SB scope */ + /* global utility methods expected within the \_SB scope */ #include <arch/x86/acpi/globutil.asl> /* Describe IRQ Routing mapping for this platform (within the \_SB scope) */ diff --git a/src/mainboard/amd/parmer/acpi/gpe.asl b/src/mainboard/amd/parmer/acpi/gpe.asl index 8e7840fad5..32d5a2a321 100644 --- a/src/mainboard/amd/parmer/acpi/gpe.asl +++ b/src/mainboard/amd/parmer/acpi/gpe.asl @@ -72,4 +72,4 @@ Scope(\_GPE) { /* Start Scope GPE */ Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ } -} /* End Scope GPE */ +} /* End Scope GPE */ diff --git a/src/mainboard/amd/parmer/acpi/sleep.asl b/src/mainboard/amd/parmer/acpi/sleep.asl index 947a2f2d43..d516ccedb0 100644 --- a/src/mainboard/amd/parmer/acpi/sleep.asl +++ b/src/mainboard/amd/parmer/acpi/sleep.asl @@ -44,7 +44,7 @@ Method(\_PTS, 1) { /* On older chips, clear PciExpWakeDisEn */ /*if (LLessEqual(\_SB.SBRI, 0x13)) { - * Store(0,\_SB.PWDE) + * Store(0,\_SB.PWDE) *} */ diff --git a/src/mainboard/amd/persimmon/acpi/gpe.asl b/src/mainboard/amd/persimmon/acpi/gpe.asl index 2f22758712..30e6fdcb3c 100644 --- a/src/mainboard/amd/persimmon/acpi/gpe.asl +++ b/src/mainboard/amd/persimmon/acpi/gpe.asl @@ -72,7 +72,7 @@ Scope(\_GPE) { /* Start Scope GPE */ Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ } -} /* End Scope GPE */ +} /* End Scope GPE */ /* Contains the GPEs for USB overcurrent */ #include "usb_oc.asl" diff --git a/src/mainboard/amd/persimmon/acpi/sleep.asl b/src/mainboard/amd/persimmon/acpi/sleep.asl index 0069aa9db2..47de049dbc 100644 --- a/src/mainboard/amd/persimmon/acpi/sleep.asl +++ b/src/mainboard/amd/persimmon/acpi/sleep.asl @@ -49,7 +49,7 @@ Method(\_PTS, 1) { /* On older chips, clear PciExpWakeDisEn */ /*if (LLessEqual(\_SB.SBRI, 0x13)) { - * Store(0,\_SB.PWDE) + * Store(0,\_SB.PWDE) *} */ diff --git a/src/mainboard/amd/thatcher/acpi/gpe.asl b/src/mainboard/amd/thatcher/acpi/gpe.asl index 8e7840fad5..32d5a2a321 100644 --- a/src/mainboard/amd/thatcher/acpi/gpe.asl +++ b/src/mainboard/amd/thatcher/acpi/gpe.asl @@ -72,4 +72,4 @@ Scope(\_GPE) { /* Start Scope GPE */ Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ } -} /* End Scope GPE */ +} /* End Scope GPE */ diff --git a/src/mainboard/amd/thatcher/acpi/sleep.asl b/src/mainboard/amd/thatcher/acpi/sleep.asl index 1dc590f484..9dd24e42b3 100644 --- a/src/mainboard/amd/thatcher/acpi/sleep.asl +++ b/src/mainboard/amd/thatcher/acpi/sleep.asl @@ -44,7 +44,7 @@ Method(\_PTS, 1) { /* On older chips, clear PciExpWakeDisEn */ /*if (LLessEqual(\_SB.SBRI, 0x13)) { - * Store(0,\_SB.PWDE) + * Store(0,\_SB.PWDE) *} */ diff --git a/src/mainboard/amd/tilapia_fam10/devicetree.cb b/src/mainboard/amd/tilapia_fam10/devicetree.cb index 77fd875ada..06e33f728d 100644 --- a/src/mainboard/amd/tilapia_fam10/devicetree.cb +++ b/src/mainboard/amd/tilapia_fam10/devicetree.cb @@ -10,7 +10,7 @@ chip northbridge/amd/amdfam10/root_complex chip northbridge/amd/amdfam10 device pci 18.0 on # northbridge chip southbridge/amd/rs780 - device pci 0.0 on end # HT 0x9600 + device pci 0.0 on end # HT 0x9600 device pci 1.0 on end # Internal Graphics P2P bridge 0x9602 device pci 2.0 on end # PCIE P2P bridge (external graphics) 0x9603 device pci 3.0 on end # PCIE P2P bridge 0x960b @@ -41,7 +41,7 @@ chip northbridge/amd/amdfam10/root_complex device pci 13.0 on end # USB device pci 13.1 on end # USB device pci 13.2 on end # USB - device pci 14.0 on # SM + device pci 14.0 on # SM chip drivers/generic/generic #dimm 0-0-0 device i2c 50 on end end diff --git a/src/mainboard/amd/tilapia_fam10/dsdt.asl b/src/mainboard/amd/tilapia_fam10/dsdt.asl index 51128bb218..2151222033 100644 --- a/src/mainboard/amd/tilapia_fam10/dsdt.asl +++ b/src/mainboard/amd/tilapia_fam10/dsdt.asl @@ -239,9 +239,9 @@ DefinitionBlock ( PWMK, 1, PWNS, 1, - /* Offset(0x61), */ /* Options_1 */ - /* ,7, */ - /* R617,1, */ + /* Offset(0x61), */ /* Options_1 */ + /* ,7, */ + /* R617,1, */ Offset(0x65), /* UsbPMControl */ , 4, @@ -837,7 +837,7 @@ DefinitionBlock ( /* On older chips, clear PciExpWakeDisEn */ /*if (LLessEqual(\_SB.SBRI, 0x13)) { - * Store(0,\_SB.PWDE) + * Store(0,\_SB.PWDE) *} */ @@ -853,13 +853,13 @@ DefinitionBlock ( * used, so it could be removed. * * - * \_GTS OEM Going To Sleep method + * \_GTS OEM Going To Sleep method * - * Entry: - * Arg0=The value of the sleeping state S1=1, S2=2 + * Entry: + * Arg0=The value of the sleeping state S1=1, S2=2 * - * Exit: - * -none- + * Exit: + * -none- * * Method(\_GTS, 1) { * DBGO("\\_GTS\n") @@ -1026,7 +1026,7 @@ DefinitionBlock ( /* PCIe HotPlug event */ /* Method(_L0F) { - * DBGO("\\_GPE\\_L0F\n") + * DBGO("\\_GPE\\_L0F\n") * } */ @@ -1049,19 +1049,19 @@ DefinitionBlock ( /* GPM0 SCI event - Moved to USB.asl */ /* Method(_L13) { - * DBGO("\\_GPE\\_L13\n") + * DBGO("\\_GPE\\_L13\n") * } */ /* GPM1 SCI event - Moved to USB.asl */ /* Method(_L14) { - * DBGO("\\_GPE\\_L14\n") + * DBGO("\\_GPE\\_L14\n") * } */ /* GPM2 SCI event - Moved to USB.asl */ /* Method(_L15) { - * DBGO("\\_GPE\\_L15\n") + * DBGO("\\_GPE\\_L15\n") * } */ @@ -1073,7 +1073,7 @@ DefinitionBlock ( /* GPM8 SCI event - Moved to USB.asl */ /* Method(_L17) { - * DBGO("\\_GPE\\_L17\n") + * DBGO("\\_GPE\\_L17\n") * } */ @@ -1090,7 +1090,7 @@ DefinitionBlock ( /* GPM4 SCI event - Moved to USB.asl */ /* Method(_L19) { - * DBGO("\\_GPE\\_L19\n") + * DBGO("\\_GPE\\_L19\n") * } */ @@ -1121,7 +1121,7 @@ DefinitionBlock ( /* GPIO2 or GPIO66 SCI event */ /* Method(_L1E) { - * DBGO("\\_GPE\\_L1E\n") + * DBGO("\\_GPE\\_L1E\n") * } */ @@ -1131,7 +1131,7 @@ DefinitionBlock ( * } */ - } /* End Scope GPE */ + } /* End Scope GPE */ #include "acpi/usb.asl" @@ -1521,7 +1521,7 @@ DefinitionBlock ( #if 0 Memory32Fixed(READWRITE, 0, 0xA0000, BSMM) - Memory32Fixed(READONLY, 0x000A0000, 0x00020000, VGAM) /* VGA memory space */ + Memory32Fixed(READONLY, 0x000A0000, 0x00020000, VGAM) /* VGA memory space */ Memory32Fixed(READONLY, 0x000C0000, 0x00020000, EMM1) /* Assume C0000-E0000 empty */ Memory32Fixed(READONLY, 0x000E0000, 0x00020000, RDBS) /* BIOS ROM area */ @@ -1655,7 +1655,7 @@ DefinitionBlock ( /* On older chips, clear PciExpWakeDisEn */ /*if (LLessEqual(\SBRI, 0x13)) { - * Store(0,\PWDE) + * Store(0,\PWDE) * } */ } /* End Method(_SB._INI) */ diff --git a/src/mainboard/amd/tilapia_fam10/mainboard.c b/src/mainboard/amd/tilapia_fam10/mainboard.c index 44c1df69ba..5e112158c2 100644 --- a/src/mainboard/amd/tilapia_fam10/mainboard.c +++ b/src/mainboard/amd/tilapia_fam10/mainboard.c @@ -24,8 +24,8 @@ #include "southbridge/amd/sb700/smbus.h" #include "southbridge/amd/rs780/rs780.h" -#define ADT7461_ADDRESS 0x4C -#define ARA_ADDRESS 0x0C /* Alert Response Address */ +#define ADT7461_ADDRESS 0x4C +#define ARA_ADDRESS 0x0C /* Alert Response Address */ #define ADT7461_read_byte(address) \ do_smbus_read_byte(SMBUS_IO_BASE, ADT7461_ADDRESS, address) @@ -150,7 +150,7 @@ static void set_gpio40_gfx(void) dword = pci_read_config32(sm_dev, 0xfc); dword &= ~(1 << 10); - /* When the gpio40 is configured as GPIO, this will represent the output value*/ + /* When the gpio40 is configured as GPIO, this will represent the output value*/ /* 1 :enable two x8 , 0 : master slot enable only */ dword |= (1 << 26); pci_write_config32(sm_dev, 0xfc, dword); @@ -162,7 +162,7 @@ static void set_gpio40_gfx(void) dword = pci_read_config32(sm_dev, 0xfc); dword &= ~(1 << 10); - /* When the gpio40 is configured as GPIO, this will represent the output value*/ + /* When the gpio40 is configured as GPIO, this will represent the output value*/ /* 1 :enable two x8 , 0 : master slot enable only */ dword &= ~(1 << 26); pci_write_config32(sm_dev, 0xfc, dword); diff --git a/src/mainboard/amd/torpedo/devicetree.cb b/src/mainboard/amd/torpedo/devicetree.cb index 2ce1dfd29e..2adfb27274 100644 --- a/src/mainboard/amd/torpedo/devicetree.cb +++ b/src/mainboard/amd/torpedo/devicetree.cb @@ -13,56 +13,56 @@ # GNU General Public License for more details. # chip northbridge/amd/agesa/family12/root_complex - device cpu_cluster 0 on - chip cpu/amd/agesa/family12 - device lapic 0 on end - end - end - device domain 0 on - subsystemid 0x1022 0x1705 inherit - chip northbridge/amd/agesa/family12 # CPU side of HT root complex - chip northbridge/amd/agesa/family12 # PCI side of HT root complex - device pci 0.0 on end # Root Complex - device pci 1.0 on end # Internal Graphics Bridge - device pci 1.1 on end # Audio Controller - device pci 2.0 on end # Root Port - device pci 3.0 on end # Root Port - device pci 4.0 on end # PCIE P2P bridge - device pci 5.0 on end # PCIE P2P bridge - device pci 6.0 on end # PCIE P2P bridge - device pci 7.0 on end # PCIE P2P bridge - device pci 8.0 on end # NB/SB Link P2P bridge - end # agesa northbridge - chip southbridge/amd/cimx/sb900 # it is under NB/SB Link, but on the same pri bus - device pci 10.0 on end # USB XHCI - device pci 10.1 on end # USB XHCI - device pci 11.0 on end # SATA - device pci 12.0 on end # USB - device pci 12.2 on end # USB - device pci 13.0 on end # USB - device pci 13.2 on end # USB - device pci 14.0 on # SM - chip drivers/generic/generic #dimm 0-0-0 - device i2c 50 on end - end - chip drivers/generic/generic #dimm 0-0-1 - device i2c 51 on end - end - end # SM - device pci 14.1 on end # IDE - device pci 14.2 on end # HDA - device pci 14.3 on # LPC - chip superio/smsc/kbc1100 - device pnp 2e.7 on # Keyboard - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - irq 0x72 = 12 - end - end # kbc1100 - end #LPC + device cpu_cluster 0 on + chip cpu/amd/agesa/family12 + device lapic 0 on end + end + end + device domain 0 on + subsystemid 0x1022 0x1705 inherit + chip northbridge/amd/agesa/family12 # CPU side of HT root complex + chip northbridge/amd/agesa/family12 # PCI side of HT root complex + device pci 0.0 on end # Root Complex + device pci 1.0 on end # Internal Graphics Bridge + device pci 1.1 on end # Audio Controller + device pci 2.0 on end # Root Port + device pci 3.0 on end # Root Port + device pci 4.0 on end # PCIE P2P bridge + device pci 5.0 on end # PCIE P2P bridge + device pci 6.0 on end # PCIE P2P bridge + device pci 7.0 on end # PCIE P2P bridge + device pci 8.0 on end # NB/SB Link P2P bridge + end # agesa northbridge + chip southbridge/amd/cimx/sb900 # it is under NB/SB Link, but on the same pri bus + device pci 10.0 on end # USB XHCI + device pci 10.1 on end # USB XHCI + device pci 11.0 on end # SATA + device pci 12.0 on end # USB + device pci 12.2 on end # USB + device pci 13.0 on end # USB + device pci 13.2 on end # USB + device pci 14.0 on # SM + chip drivers/generic/generic #dimm 0-0-0 + device i2c 50 on end + end + chip drivers/generic/generic #dimm 0-0-1 + device i2c 51 on end + end + end # SM + device pci 14.1 on end # IDE + device pci 14.2 on end # HDA + device pci 14.3 on # LPC + chip superio/smsc/kbc1100 + device pnp 2e.7 on # Keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + irq 0x72 = 12 + end + end # kbc1100 + end #LPC device pci 14.4 on end # PCI bridge - device pci 14.5 on end # USB 2 + device pci 14.5 on end # USB 2 device pci 14.6 on end # Ethernet Controller device pci 14.7 on end # SD Flash Controller device pci 15.0 on end # PCIe PortA @@ -70,16 +70,16 @@ chip northbridge/amd/agesa/family12/root_complex device pci 15.2 on end # PCIe PortC device pci 15.3 on end # PCIe PortD register "gpp_configuration" = "4" #1:1:1:1 - register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE + register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE end #southbridge/amd/cimx/sb900 - device pci 18.0 on end - device pci 18.1 on end - device pci 18.2 on end - device pci 18.3 on end - device pci 18.4 on end - device pci 18.5 on end - device pci 18.6 on end - device pci 18.7 on end - end #chip northbridge/amd/agesa/family12 # CPU side of HT root complex - end #domain + device pci 18.0 on end + device pci 18.1 on end + device pci 18.2 on end + device pci 18.3 on end + device pci 18.4 on end + device pci 18.5 on end + device pci 18.6 on end + device pci 18.7 on end + end #chip northbridge/amd/agesa/family12 # CPU side of HT root complex + end #domain end #northbridge/amd/agesa/family12/root_complex diff --git a/src/mainboard/amd/torpedo/dsdt.asl b/src/mainboard/amd/torpedo/dsdt.asl index 0c55ff4c1b..4ee5fb4ad7 100644 --- a/src/mainboard/amd/torpedo/dsdt.asl +++ b/src/mainboard/amd/torpedo/dsdt.asl @@ -676,7 +676,7 @@ DefinitionBlock ( /* On older chips, clear PciExpWakeDisEn */ /*if (LLessEqual(\_SB.SBRI, 0x13)) { - * Store(0,\_SB.PWDE) + * Store(0,\_SB.PWDE) *} */ @@ -691,13 +691,13 @@ DefinitionBlock ( * used, so it could be removed. * * - * \_GTS OEM Going To Sleep method + * \_GTS OEM Going To Sleep method * - * Entry: - * Arg0=The value of the sleeping state S1=1, S2=2 + * Entry: + * Arg0=The value of the sleeping state S1=1, S2=2 * - * Exit: - * -none- + * Exit: + * -none- * * Method(\_GTS, 1) { * DBGO("\\_GTS\n") @@ -766,7 +766,7 @@ DefinitionBlock ( } /* End Method(\_WAK) */ Scope(\_GPE) { /* Start Scope GPE */ - } /* End Scope GPE */ + } /* End Scope GPE */ /* System Bus */ Scope(\_SB) { /* Start \_SB scope */ diff --git a/src/mainboard/amd/torpedo/gpio.c b/src/mainboard/amd/torpedo/gpio.c index 5a77dc0de0..e26052a734 100644 --- a/src/mainboard/amd/torpedo/gpio.c +++ b/src/mainboard/amd/torpedo/gpio.c @@ -75,7 +75,7 @@ void gpioEarlyInit(void) { StripInfo = (Data8 & BIT7) >> 7; Data8 = Mmio8_G (GpioMmioAddr, GPIO_31); StripInfo |= (Data8 & BIT7) >> 6; - if (StripInfo < boardRevC) { // for old board. Rev B + if (StripInfo < boardRevC) { // for old board. Rev B Mmio8_And_Or (IoMuxMmioAddr, GPIO_111, 0x00, 3); // function 3 Mmio8_And_Or (IoMuxMmioAddr, GPIO_113, 0x00, 0); // function 0 } diff --git a/src/mainboard/asus/kfsn4-dre/acpi/pm_ctrl.asl b/src/mainboard/asus/kfsn4-dre/acpi/pm_ctrl.asl index 0afb841435..bde6fb628d 100644 --- a/src/mainboard/asus/kfsn4-dre/acpi/pm_ctrl.asl +++ b/src/mainboard/asus/kfsn4-dre/acpi/pm_ctrl.asl @@ -231,7 +231,7 @@ /* On older chips, clear PciExpWakeDisEn */ /*if (LLessEqual(\_SB.SBRI, 0x13)) { - * Store(0,\_SB.PWDE) + * Store(0,\_SB.PWDE) *} */ diff --git a/src/mainboard/asus/kfsn4-dre/dsdt.asl b/src/mainboard/asus/kfsn4-dre/dsdt.asl index 2f1e86a14b..575715cf66 100644 --- a/src/mainboard/asus/kfsn4-dre/dsdt.asl +++ b/src/mainboard/asus/kfsn4-dre/dsdt.asl @@ -126,7 +126,7 @@ DefinitionBlock ( Notify (\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ } - } /* End Scope GPE */ + } /* End Scope GPE */ /* Root of the bus hierarchy */ Scope (\_SB) diff --git a/src/mainboard/asus/kfsn4-dre/resourcemap.c b/src/mainboard/asus/kfsn4-dre/resourcemap.c index cfbade68f2..f4e549b17f 100644 --- a/src/mainboard/asus/kfsn4-dre/resourcemap.c +++ b/src/mainboard/asus/kfsn4-dre/resourcemap.c @@ -226,7 +226,7 @@ static void setup_mb_resource_map(void) * This field defines the start of PCI I/O region n * [31:25] Reserved */ -// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC0), 0xFE000FCC, 0x00001013, +// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC0), 0xFE000FCC, 0x00001013, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC8), 0xFE000FCC, 0x00000000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD0), 0xFE000FCC, 0x00000000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD8), 0xFE000FCC, 0x00000000, diff --git a/src/mainboard/asus/kfsn4-dre/romstage.c b/src/mainboard/asus/kfsn4-dre/romstage.c index 56a6bdffd5..2809f0fe91 100644 --- a/src/mainboard/asus/kfsn4-dre/romstage.c +++ b/src/mainboard/asus/kfsn4-dre/romstage.c @@ -318,8 +318,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) * IS_ENABLED(CONFIG_DEBUG_SMBUS) uncomment this block */ if (IS_ENABLED(CONFIG_DEBUG_SMBUS)) { - dump_spd_registers(&cpu[0]); - dump_smbus_registers(); + dump_spd_registers(&cpu[0]); + dump_smbus_registers(); } #endif @@ -344,8 +344,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) /* Initialize GPIO */ /* Access SuperIO GPI03 logical device */ uint16_t port = GPIO3_DEV >> 8; - outb(0x87, port); - outb(0x87, port); + outb(0x87, port); + outb(0x87, port); pnp_set_logical_device(GPIO3_DEV); /* Set GP37 (power LED) to output */ pnp_write_config(GPIO3_DEV, 0xf0, 0x7f); diff --git a/src/mainboard/asus/p3b-f/devicetree.cb b/src/mainboard/asus/p3b-f/devicetree.cb index 5bee5ae96a..bc9ad17c93 100644 --- a/src/mainboard/asus/p3b-f/devicetree.cb +++ b/src/mainboard/asus/p3b-f/devicetree.cb @@ -1,59 +1,59 @@ chip northbridge/intel/i440bx # Northbridge - device cpu_cluster 0 on # APIC cluster - chip cpu/intel/slot_1 # CPU - device lapic 0 on end # APIC - end - end - device domain 0 on # PCI domain - device pci 0.0 on end # Host bridge - device pci 1.0 on end # PCI/AGP bridge - chip southbridge/intel/i82371eb # Southbridge - device pci 4.0 on # ISA bridge - chip superio/winbond/w83977tf # Super I/O (FIXME: It's W83977EF!) - device pnp 3f0.0 on # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 3f0.1 on # Parallel port - io 0x60 = 0x378 - irq 0x70 = 7 - end - device pnp 3f0.2 on # COM1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 3f0.3 on # COM2 / IR - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 3f0.5 on # PS/2 keyboard - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 # PS/2 keyboard interrupt - irq 0x72 = 12 # PS/2 mouse interrupt - end - device pnp 3f0.6 on # Consumer IR - end - device pnp 3f0.7 on # GPIO 1 - end - device pnp 3f0.8 on # GPIO 2 - end - device pnp 3f0.a on # ACPI - end - end - end - device pci 4.1 on end # IDE - device pci 4.2 on end # USB - device pci 4.3 on end # ACPI - register "ide0_enable" = "1" - register "ide1_enable" = "1" - register "ide_legacy_enable" = "1" - # Enable UDMA/33 for higher speed if your IDE device(s) support it. - register "ide0_drive0_udma33_enable" = "0" - register "ide0_drive1_udma33_enable" = "0" - register "ide1_drive0_udma33_enable" = "0" - register "ide1_drive1_udma33_enable" = "0" - end - end + device cpu_cluster 0 on # APIC cluster + chip cpu/intel/slot_1 # CPU + device lapic 0 on end # APIC + end + end + device domain 0 on # PCI domain + device pci 0.0 on end # Host bridge + device pci 1.0 on end # PCI/AGP bridge + chip southbridge/intel/i82371eb # Southbridge + device pci 4.0 on # ISA bridge + chip superio/winbond/w83977tf # Super I/O (FIXME: It's W83977EF!) + device pnp 3f0.0 on # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 3f0.1 on # Parallel port + io 0x60 = 0x378 + irq 0x70 = 7 + end + device pnp 3f0.2 on # COM1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 3f0.3 on # COM2 / IR + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 3f0.5 on # PS/2 keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 # PS/2 keyboard interrupt + irq 0x72 = 12 # PS/2 mouse interrupt + end + device pnp 3f0.6 on # Consumer IR + end + device pnp 3f0.7 on # GPIO 1 + end + device pnp 3f0.8 on # GPIO 2 + end + device pnp 3f0.a on # ACPI + end + end + end + device pci 4.1 on end # IDE + device pci 4.2 on end # USB + device pci 4.3 on end # ACPI + register "ide0_enable" = "1" + register "ide1_enable" = "1" + register "ide_legacy_enable" = "1" + # Enable UDMA/33 for higher speed if your IDE device(s) support it. + register "ide0_drive0_udma33_enable" = "0" + register "ide0_drive1_udma33_enable" = "0" + register "ide1_drive0_udma33_enable" = "0" + register "ide1_drive1_udma33_enable" = "0" + end + end end diff --git a/src/mainboard/avalue/eax-785e/devicetree.cb b/src/mainboard/avalue/eax-785e/devicetree.cb index 42ddf01d7f..2bf3ca9c00 100644 --- a/src/mainboard/avalue/eax-785e/devicetree.cb +++ b/src/mainboard/avalue/eax-785e/devicetree.cb @@ -41,49 +41,49 @@ chip northbridge/amd/amdfam10/root_complex device pci 13.0 on end # USB device pci 13.2 on end # USB device pci 14.0 on end # SM - device pci 14.1 on end # IDE 0x439c - device pci 14.2 on end # HDA 0x4383 + device pci 14.1 on end # IDE 0x439c + device pci 14.2 on end # HDA 0x4383 device pci 14.3 on - chip superio/winbond/w83627hf - device pnp 2e.0 off # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 2e.1 off # Parallel Port - io 0x60 = 0x378 - irq 0x70 = 7 - end - device pnp 2e.2 on # Com1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.3 on # Com2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.5 on # PS/2 Keyboard & mouse - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - irq 0x72 = 12 - end - device pnp 2e.6 off # SFI - io 0x62 = 0x100 - end - device pnp 2e.7 off # GPIO_GAME_MIDI - io 0x60 = 0x220 - io 0x62 = 0x300 - irq 0x70 = 9 - end - device pnp 2e.8 off end # WDTO_PLED - device pnp 2e.9 off end # GPIO_SUSLED - device pnp 2e.a off end # ACPI - device pnp 2e.b on # HW Monitor - io 0x60 = 0x290 - irq 0x70 = 5 - end - end #superio/winbond/w83627hf + chip superio/winbond/w83627hf + device pnp 2e.0 off # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 2e.1 off # Parallel Port + io 0x60 = 0x378 + irq 0x70 = 7 + end + device pnp 2e.2 on # Com1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.3 on # Com2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.5 on # PS/2 Keyboard & mouse + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + irq 0x72 = 12 + end + device pnp 2e.6 off # SFI + io 0x62 = 0x100 + end + device pnp 2e.7 off # GPIO_GAME_MIDI + io 0x60 = 0x220 + io 0x62 = 0x300 + irq 0x70 = 9 + end + device pnp 2e.8 off end # WDTO_PLED + device pnp 2e.9 off end # GPIO_SUSLED + device pnp 2e.a off end # ACPI + device pnp 2e.b on # HW Monitor + io 0x60 = 0x290 + irq 0x70 = 5 + end + end #superio/winbond/w83627hf end # LPC 0x439d device pci 14.4 on end # PCIB 0x4384, NOTE: PCI interface pins shared with GPIO {GPIO 35:0} device pci 14.5 on end # USB 2 diff --git a/src/mainboard/intel/saddlebrook/devicetree.cb b/src/mainboard/intel/saddlebrook/devicetree.cb index 43d14ede49..71fed875de 100644 --- a/src/mainboard/intel/saddlebrook/devicetree.cb +++ b/src/mainboard/intel/saddlebrook/devicetree.cb @@ -62,7 +62,7 @@ chip soc/intel/skylake # Determines if enable Serial IRQ. Values 0: Disabled, 1: Enabled register "SerialIrqConfigSirqEnable" = "0x01" - register "SerialIrqConfigSirqMode" = "0x01" + register "SerialIrqConfigSirqMode" = "0x01" # VR Settings Configuration for 5 Domains #+----------------+-------+-------+-------------+-------------+-------+ @@ -226,17 +226,17 @@ chip soc/intel/skylake [7] = 1, \ }" register "SerialIoDevMode" = "{ \ - [PchSerialIoIndexI2C0] = PchSerialIoPci, \ - [PchSerialIoIndexI2C1] = PchSerialIoPci, \ - [PchSerialIoIndexI2C2] = PchSerialIoPci, \ - [PchSerialIoIndexI2C3] = PchSerialIoPci, \ - [PchSerialIoIndexI2C4] = PchSerialIoPci, \ - [PchSerialIoIndexI2C5] = PchSerialIoPci, \ - [PchSerialIoIndexSpi0] = PchSerialIoPci, \ - [PchSerialIoIndexSpi1] = PchSerialIoPci, \ - [PchSerialIoIndexUart0] = PchSerialIoPci, \ - [PchSerialIoIndexUart1] = PchSerialIoPci, \ - [PchSerialIoIndexUart2] = PchSerialIoSkipInit, \ + [PchSerialIoIndexI2C0] = PchSerialIoPci, \ + [PchSerialIoIndexI2C1] = PchSerialIoPci, \ + [PchSerialIoIndexI2C2] = PchSerialIoPci, \ + [PchSerialIoIndexI2C3] = PchSerialIoPci, \ + [PchSerialIoIndexI2C4] = PchSerialIoPci, \ + [PchSerialIoIndexI2C5] = PchSerialIoPci, \ + [PchSerialIoIndexSpi0] = PchSerialIoPci, \ + [PchSerialIoIndexSpi1] = PchSerialIoPci, \ + [PchSerialIoIndexUart0] = PchSerialIoPci, \ + [PchSerialIoIndexUart1] = PchSerialIoPci, \ + [PchSerialIoIndexUart2] = PchSerialIoSkipInit, \ }" # PL2 override 25W diff --git a/src/mainboard/lenovo/t400/devicetree.cb b/src/mainboard/lenovo/t400/devicetree.cb index 416906f03e..0c72c86ed5 100644 --- a/src/mainboard/lenovo/t400/devicetree.cb +++ b/src/mainboard/lenovo/t400/devicetree.cb @@ -237,7 +237,7 @@ chip northbridge/intel/gm45 device pci 1f.3 on # SMBus subsystemid 0x17aa 0x20f9 ioapic_irq 2 INTC 0x12 - # eeprom, 8 virtual devices, same chip + # eeprom, 8 virtual devices, same chip chip drivers/i2c/at24rf08c device i2c 54 on end device i2c 55 on end diff --git a/src/mainboard/lenovo/t520/variants/t520/devicetree.cb b/src/mainboard/lenovo/t520/variants/t520/devicetree.cb index f03b87e6c0..6decf9bebb 100644 --- a/src/mainboard/lenovo/t520/variants/t520/devicetree.cb +++ b/src/mainboard/lenovo/t520/variants/t520/devicetree.cb @@ -151,7 +151,7 @@ chip northbridge/intel/sandybridge end # LPC bridge device pci 1f.2 on end # SATA Controller 1 device pci 1f.3 on # SMBUS controller - # eeprom, 8 virtual devices, same chip + # eeprom, 8 virtual devices, same chip chip drivers/i2c/at24rf08c device i2c 54 on end device i2c 55 on end diff --git a/src/mainboard/lenovo/t520/variants/w520/devicetree.cb b/src/mainboard/lenovo/t520/variants/w520/devicetree.cb index b69b66c2fa..33b9368f50 100644 --- a/src/mainboard/lenovo/t520/variants/w520/devicetree.cb +++ b/src/mainboard/lenovo/t520/variants/w520/devicetree.cb @@ -151,7 +151,7 @@ chip northbridge/intel/sandybridge end # LPC bridge device pci 1f.2 on end # SATA Controller 1 device pci 1f.3 on # SMBUS controller - # eeprom, 8 virtual devices, same chip + # eeprom, 8 virtual devices, same chip chip drivers/i2c/at24rf08c device i2c 54 on end device i2c 55 on end diff --git a/src/mainboard/lenovo/t530/variants/t530/devicetree.cb b/src/mainboard/lenovo/t530/variants/t530/devicetree.cb index a28c177572..3103762b0f 100644 --- a/src/mainboard/lenovo/t530/variants/t530/devicetree.cb +++ b/src/mainboard/lenovo/t530/variants/t530/devicetree.cb @@ -158,7 +158,7 @@ chip northbridge/intel/sandybridge end # LPC bridge device pci 1f.2 on end # SATA Controller 1 device pci 1f.3 on - # eeprom, 8 virtual devices, same chip + # eeprom, 8 virtual devices, same chip chip drivers/i2c/at24rf08c device i2c 54 on end device i2c 55 on end diff --git a/src/mainboard/lenovo/t530/variants/w530/devicetree.cb b/src/mainboard/lenovo/t530/variants/w530/devicetree.cb index 2a22d4e268..d9d9df5e14 100644 --- a/src/mainboard/lenovo/t530/variants/w530/devicetree.cb +++ b/src/mainboard/lenovo/t530/variants/w530/devicetree.cb @@ -10,12 +10,12 @@ chip northbridge/intel/sandybridge register "gpu_dp_c_hotplug" = "0" # Enable Panel as LVDS and configure power delays - register "gpu_panel_port_select" = "0" # LVDS - register "gpu_panel_power_cycle_delay" = "6" # T7: 500ms - register "gpu_panel_power_up_delay" = "100" # T1+T2: 10ms - register "gpu_panel_power_down_delay" = "100" # T5+T6: 10ms - register "gpu_panel_power_backlight_off_delay" = "2000" # T4: 200ms - register "gpu_panel_power_backlight_on_delay" = "2000" # T3: 200ms + register "gpu_panel_port_select" = "0" # LVDS + register "gpu_panel_power_cycle_delay" = "6" # T7: 500ms + register "gpu_panel_power_up_delay" = "100" # T1+T2: 10ms + register "gpu_panel_power_down_delay" = "100" # T5+T6: 10ms + register "gpu_panel_power_backlight_off_delay" = "2000" # T4: 200ms + register "gpu_panel_power_backlight_on_delay" = "2000" # T3: 200ms register "gfx.use_spread_spectrum_clock" = "1" register "gfx.link_frequency_270_mhz" = "1" register "gpu_cpu_backlight" = "0x1155" diff --git a/src/mainboard/lenovo/t60/devicetree.cb b/src/mainboard/lenovo/t60/devicetree.cb index aab647fa11..053b9d30cb 100644 --- a/src/mainboard/lenovo/t60/devicetree.cb +++ b/src/mainboard/lenovo/t60/devicetree.cb @@ -221,7 +221,7 @@ chip northbridge/intel/i945 0x54, 0xff, 0xff, 0x07 }" device i2c 69 on end end - # eeprom, 8 virtual devices, same chip + # eeprom, 8 virtual devices, same chip chip drivers/i2c/at24rf08c device i2c 54 on end device i2c 55 on end diff --git a/src/mainboard/lenovo/x1_carbon_gen1/devicetree.cb b/src/mainboard/lenovo/x1_carbon_gen1/devicetree.cb index cb2d8f3b89..49e5933f5f 100644 --- a/src/mainboard/lenovo/x1_carbon_gen1/devicetree.cb +++ b/src/mainboard/lenovo/x1_carbon_gen1/devicetree.cb @@ -126,7 +126,7 @@ chip northbridge/intel/sandybridge end chip drivers/pc80/tpm - device pnp 0c31.0 on end + device pnp 0c31.0 on end end chip ec/lenovo/h8 @@ -166,7 +166,7 @@ chip northbridge/intel/sandybridge end # SATA Controller 1 device pci 1f.3 on subsystemid 0x17aa 0x21f9 - # eeprom, 8 virtual devices, same chip + # eeprom, 8 virtual devices, same chip chip drivers/i2c/at24rf08c device i2c 54 on end device i2c 55 on end diff --git a/src/mainboard/lenovo/x200/devicetree.cb b/src/mainboard/lenovo/x200/devicetree.cb index 3bc3159c83..b74f25a65d 100644 --- a/src/mainboard/lenovo/x200/devicetree.cb +++ b/src/mainboard/lenovo/x200/devicetree.cb @@ -211,7 +211,7 @@ chip northbridge/intel/gm45 device pci 1f.3 on # SMBus subsystemid 0x17aa 0x20f9 ioapic_irq 2 INTC 0x12 - # eeprom, 8 virtual devices, same chip + # eeprom, 8 virtual devices, same chip chip drivers/i2c/at24rf08c device i2c 54 on end device i2c 55 on end diff --git a/src/mainboard/lenovo/x201/devicetree.cb b/src/mainboard/lenovo/x201/devicetree.cb index de5775558e..a1746bdee8 100644 --- a/src/mainboard/lenovo/x201/devicetree.cb +++ b/src/mainboard/lenovo/x201/devicetree.cb @@ -165,7 +165,7 @@ chip northbridge/intel/nehalem end device pci 1f.3 on # SMBUS subsystemid 0x17aa 0x2167 - # eeprom, 8 virtual devices, same chip + # eeprom, 8 virtual devices, same chip chip drivers/i2c/at24rf08c device i2c 54 on end device i2c 55 on end diff --git a/src/mainboard/lenovo/x220/devicetree.cb b/src/mainboard/lenovo/x220/devicetree.cb index ae2a03ec09..a96026601f 100644 --- a/src/mainboard/lenovo/x220/devicetree.cb +++ b/src/mainboard/lenovo/x220/devicetree.cb @@ -177,7 +177,7 @@ chip northbridge/intel/sandybridge end # SATA Controller 1 device pci 1f.3 on subsystemid 0x17aa 0x21db - # eeprom, 8 virtual devices, same chip + # eeprom, 8 virtual devices, same chip chip drivers/i2c/at24rf08c device i2c 54 on end device i2c 55 on end diff --git a/src/mainboard/lenovo/x230/devicetree.cb b/src/mainboard/lenovo/x230/devicetree.cb index 41e13f6c75..01693c0430 100644 --- a/src/mainboard/lenovo/x230/devicetree.cb +++ b/src/mainboard/lenovo/x230/devicetree.cb @@ -132,7 +132,7 @@ chip northbridge/intel/sandybridge end chip drivers/pc80/tpm - device pnp 0c31.0 on end + device pnp 0c31.0 on end end chip ec/lenovo/h8 @@ -179,7 +179,7 @@ chip northbridge/intel/sandybridge end # SATA Controller 1 device pci 1f.3 on subsystemid 0x17aa 0x21fa - # eeprom, 8 virtual devices, same chip + # eeprom, 8 virtual devices, same chip chip drivers/i2c/at24rf08c device i2c 54 on end device i2c 55 on end diff --git a/src/mainboard/lenovo/x60/devicetree.cb b/src/mainboard/lenovo/x60/devicetree.cb index cf319a36f3..da9bff7e41 100644 --- a/src/mainboard/lenovo/x60/devicetree.cb +++ b/src/mainboard/lenovo/x60/devicetree.cb @@ -204,7 +204,7 @@ chip northbridge/intel/i945 0x54, 0xff, 0xff, 0x07 }" device i2c 69 on end end - # eeprom, 8 virtual devices, same chip + # eeprom, 8 virtual devices, same chip chip drivers/i2c/at24rf08c device i2c 54 on end device i2c 55 on end diff --git a/src/mainboard/lenovo/z61t/devicetree.cb b/src/mainboard/lenovo/z61t/devicetree.cb index 869e970cd4..1c60e6bf6b 100644 --- a/src/mainboard/lenovo/z61t/devicetree.cb +++ b/src/mainboard/lenovo/z61t/devicetree.cb @@ -139,7 +139,6 @@ chip northbridge/intel/i945 io 0x66 = 0x1604 end - register "config0" = "0xa6" register "config1" = "0x05" register "config2" = "0xa0" @@ -212,27 +211,26 @@ chip northbridge/intel/i945 subsystemid 0x17aa 0x200d end device pci 1f.3 on # SMBUS - subsystemid 0x17aa 0x200f - chip drivers/i2c/ck505 + subsystemid 0x17aa 0x200f + chip drivers/i2c/ck505 register "mask" = "{ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff }" # vendor clockgen setup register "regs" = "{ 0x6d, 0xff, 0xff, 0x20, 0x41, 0x7f, 0x18, 0x00 }" - device i2c 69 on end - end - # eeprom, 8 virtual devices, same chip - chip drivers/i2c/at24rf08c - device i2c 54 on end - device i2c 55 on end - device i2c 56 on end - device i2c 57 on end - device i2c 5c on end - device i2c 5d on end - device i2c 5e on end - device i2c 5f on end - end - + device i2c 69 on end + end + # eeprom, 8 virtual devices, same chip + chip drivers/i2c/at24rf08c + device i2c 54 on end + device i2c 55 on end + device i2c 56 on end + device i2c 57 on end + device i2c 5c on end + device i2c 5d on end + device i2c 5e on end + device i2c 5f on end + end end end end diff --git a/src/mainboard/msi/ms7721/devicetree.cb b/src/mainboard/msi/ms7721/devicetree.cb index 7eaf78c9c9..35079255ad 100644 --- a/src/mainboard/msi/ms7721/devicetree.cb +++ b/src/mainboard/msi/ms7721/devicetree.cb @@ -47,7 +47,7 @@ chip northbridge/amd/agesa/family15tn/root_complex device pci 12.2 on end # USB EHCI device pci 13.0 on end # USB OHCI device pci 13.2 on end # USB EHCI - device pci 14.0 on # SMBUS + device pci 14.0 on # SMBUS chip drivers/generic/generic #dimm 0 device i2c 50 on end # 7-bit SPD address end @@ -57,7 +57,7 @@ chip northbridge/amd/agesa/family15tn/root_complex end # SM device pci 14.1 off end # IDE 0x439c device pci 14.2 on end # Azalia (Audio) - device pci 14.3 on # LPC 0x439d + device pci 14.3 on # LPC 0x439d chip superio/fintek/f71869ad register "multi_function_register_1" = "0x01" register "multi_function_register_2" = "0x0f" @@ -97,51 +97,51 @@ chip northbridge/amd/agesa/family15tn/root_complex io 0x60 = 0x225 # Fintek datasheet says 0x295. irq 0x70 = 0 end - device pnp 4e.05 on # KBC + device pnp 4e.05 on # KBC io 0x60 = 0x060 irq 0x70 = 1 # Keyboard IRQ irq 0x72 = 12 # Mouse IRQ end - device pnp 4e.06 on # GPIO + device pnp 4e.06 on # GPIO # ! GPIO config is disabled because the code in romstage.c # ! has already taken care of it - #io 0x60 = 0xa00 - #irq 0xe0 = 0x04 # GPIO1 output - #irq 0xe1 = 0xff # GPIO1 output data - #irq 0xe3 = 0x04 # GPIO1 drive enable - #irq 0xe4 = 0x00 # GPIO1 PME enable - #irq 0xe5 = 0x00 # GPIO1 input detect select - #irq 0xe6 = 0x40 # GPIO1 event status - - #irq 0xd0 = 0x00 # GPIO2 output - #irq 0xd1 = 0xff # GPIO2 output data - #irq 0xd3 = 0x00 # GPIO2 drive enable - - #irq 0xc0 = 0x00 # GPIO3 output - #irq 0xc1 = 0xff # GPIO3 output data - - #irq 0xb0 = 0x04 # GPIO4 output - #irq 0xb1 = 0x04 # GPIO4 output data - #irq 0xb3 = 0x04 # GPIO4 drive enable - #irq 0xb4 = 0x00 # GPIO4 PME enable - #irq 0xb5 = 0x00 # GPIO4 input detect select - #irq 0xb6 = 0x00 # GPIO4 event status - - #irq 0xa0 = 0x00 # GPIO5 output - #irq 0xa1 = 0x1f # GPIO5 output data - #irq 0xa3 = 0x00 # GPIO5 drive enable - #irq 0xa4 = 0x00 # GPIO5 PME enable - #irq 0xa5 = 0xff # GPIO5 input detect select - #irq 0xa6 = 0xe0 # GPIO5 event status - - #irq 0x90 = 0x00 # GPIO6 output - #irq 0x91 = 0xff # GPIO6 output data - #irq 0x93 = 0x00 # GPIO6 drive enable - - #irq 0x80 = 0x00 # GPIO7 output - #irq 0x81 = 0xff # GPIO7 output data - #irq 0x83 = 0x00 # GPIO7 drive enable - end + #io 0x60 = 0xa00 + #irq 0xe0 = 0x04 # GPIO1 output + #irq 0xe1 = 0xff # GPIO1 output data + #irq 0xe3 = 0x04 # GPIO1 drive enable + #irq 0xe4 = 0x00 # GPIO1 PME enable + #irq 0xe5 = 0x00 # GPIO1 input detect select + #irq 0xe6 = 0x40 # GPIO1 event status + + #irq 0xd0 = 0x00 # GPIO2 output + #irq 0xd1 = 0xff # GPIO2 output data + #irq 0xd3 = 0x00 # GPIO2 drive enable + + #irq 0xc0 = 0x00 # GPIO3 output + #irq 0xc1 = 0xff # GPIO3 output data + + #irq 0xb0 = 0x04 # GPIO4 output + #irq 0xb1 = 0x04 # GPIO4 output data + #irq 0xb3 = 0x04 # GPIO4 drive enable + #irq 0xb4 = 0x00 # GPIO4 PME enable + #irq 0xb5 = 0x00 # GPIO4 input detect select + #irq 0xb6 = 0x00 # GPIO4 event status + + #irq 0xa0 = 0x00 # GPIO5 output + #irq 0xa1 = 0x1f # GPIO5 output data + #irq 0xa3 = 0x00 # GPIO5 drive enable + #irq 0xa4 = 0x00 # GPIO5 PME enable + #irq 0xa5 = 0xff # GPIO5 input detect select + #irq 0xa6 = 0xe0 # GPIO5 event status + + #irq 0x90 = 0x00 # GPIO6 output + #irq 0x91 = 0xff # GPIO6 output data + #irq 0x93 = 0x00 # GPIO6 drive enable + + #irq 0x80 = 0x00 # GPIO7 output + #irq 0x81 = 0xff # GPIO7 output data + #irq 0x83 = 0x00 # GPIO7 drive enable + end device pnp 4e.07 on end # WDT device pnp 4e.08 off end # CIR diff --git a/src/mainboard/msi/ms9652_fam10/devicetree.cb b/src/mainboard/msi/ms9652_fam10/devicetree.cb index 51d5bf3425..c6dae6d451 100644 --- a/src/mainboard/msi/ms9652_fam10/devicetree.cb +++ b/src/mainboard/msi/ms9652_fam10/devicetree.cb @@ -13,153 +13,153 @@ ## ## This program is distributed in the hope that it will be useful, ## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ## GNU General Public License for more details. ## chip northbridge/amd/amdfam10/root_complex # Root complex - device cpu_cluster 0 on # (L)APIC cluster - chip cpu/amd/socket_F_1207 # CPU socket - device lapic 0 on end # Local APIC of the CPU - end - end - device domain 0 on # PCI domain - subsystemid 0x1462 0x9652 inherit - chip northbridge/amd/amdfam10 # Northbridge / RAM controller - device pci 18.0 on # Link 0 - chip southbridge/nvidia/mcp55 # Southbridge - device pci 0.0 on end # HT - device pci 1.0 on # LPC - chip superio/winbond/w83627ehg # Super I/O - device pnp 2e.0 on # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 2e.1 off # Parallel port - io 0x60 = 0x378 - irq 0x70 = 7 - end - device pnp 2e.2 on # Com1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.3 on # Com2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.5 on # PS/2 keyboard & mouse - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - irq 0x72 = 12 - end - device pnp 2e.106 off # Serial flash interface (SFI) - io 0x60 = 0x100 - end - device pnp 2e.007 off # GPIO 1 - end - device pnp 2e.107 on # Game port - io 0x60 = 0x220 - end - device pnp 2e.207 on # MIDI - io 0x62 = 0x330 - irq 0x70 = 0xa - end - device pnp 2e.307 off # GPIO 6 - end - device pnp 2e.8 off # WDTO#, PLED - end - device pnp 2e.009 off # GPIO 2 - end - device pnp 2e.109 off # GPIO 3 - end - device pnp 2e.209 off # GPIO 4 - end - device pnp 2e.309 off # GPIO 5 - end - device pnp 2e.a off end # ACPI - device pnp 2e.b on # Hardware monitor - io 0x60 = 0x290 - irq 0x70 = 5 - end - end - end - device pci 1.1 on # SM 0 - chip drivers/generic/generic # DIMM 0-0-0 - device i2c 50 on end - end - chip drivers/generic/generic # DIMM 0-0-1 - device i2c 51 on end - end - chip drivers/generic/generic # DIMM 0-1-0 - device i2c 52 on end - end - chip drivers/generic/generic # DIMM 0-1-1 - device i2c 53 on end - end - chip drivers/generic/generic # DIMM 1-0-0 - device i2c 54 on end - end - chip drivers/generic/generic # DIMM 1-0-1 - device i2c 55 on end - end - chip drivers/generic/generic # DIMM 1-1-0 - device i2c 56 on end - end - chip drivers/generic/generic # DIMM 1-1-1 - device i2c 57 on end - end - end - device pci 1.1 on # SM 1 - # PCI device SMBus address will - # depend on addon PCI device, do - # we need to scan_smbus_bus? - # chip drivers/generic/generic # PCIXA slot 1 - # device i2c 50 on end - # end - # chip drivers/generic/generic # PCIXB slot 1 - # device i2c 51 on end - # end - # chip drivers/generic/generic # PCIXB slot 2 - # device i2c 52 on end - # end - # chip drivers/generic/generic # PCI slot 1 - # device i2c 53 on end - # end - # chip drivers/generic/generic # Master MCP55 PCI-E - # device i2c 54 on end - # end - # chip drivers/generic/generic # Slave MCP55 PCI-E - # device i2c 55 on end - # end - # chip drivers/generic/generic # MAC EEPROM - # device i2c 51 on end - # end - end - device pci 2.0 on end # USB 1.1 - device pci 2.1 on end # USB 2 - device pci 4.0 on end # IDE - device pci 5.0 on end # SATA 0 - device pci 5.1 on end # SATA 1 - device pci 5.2 on end # SATA 2 - device pci 6.1 on end # AZA - device pci 8.0 on end # NIC - device pci 9.0 on end # NIC - register "ide0_enable" = "1" - register "sata0_enable" = "1" - register "sata1_enable" = "1" - # 1: SMBus under 2e.8, 2: SM0 3: SM1 - register "mac_eeprom_smbus" = "3" - register "mac_eeprom_addr" = "0x51" - end - end - device pci 18.0 on end # HT 1.0 - device pci 18.0 on end # HT 2.0 - device pci 18.1 on end - device pci 18.2 on end - device pci 18.3 on end - device pci 18.4 on end - end - end + device cpu_cluster 0 on # (L)APIC cluster + chip cpu/amd/socket_F_1207 # CPU socket + device lapic 0 on end # Local APIC of the CPU + end + end + device domain 0 on # PCI domain + subsystemid 0x1462 0x9652 inherit + chip northbridge/amd/amdfam10 # Northbridge / RAM controller + device pci 18.0 on # Link 0 + chip southbridge/nvidia/mcp55 # Southbridge + device pci 0.0 on end # HT + device pci 1.0 on # LPC + chip superio/winbond/w83627ehg # Super I/O + device pnp 2e.0 on # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 2e.1 off # Parallel port + io 0x60 = 0x378 + irq 0x70 = 7 + end + device pnp 2e.2 on # Com1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.3 on # Com2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.5 on # PS/2 keyboard & mouse + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + irq 0x72 = 12 + end + device pnp 2e.106 off # Serial flash interface (SFI) + io 0x60 = 0x100 + end + device pnp 2e.007 off # GPIO 1 + end + device pnp 2e.107 on # Game port + io 0x60 = 0x220 + end + device pnp 2e.207 on # MIDI + io 0x62 = 0x330 + irq 0x70 = 0xa + end + device pnp 2e.307 off # GPIO 6 + end + device pnp 2e.8 off # WDTO#, PLED + end + device pnp 2e.009 off # GPIO 2 + end + device pnp 2e.109 off # GPIO 3 + end + device pnp 2e.209 off # GPIO 4 + end + device pnp 2e.309 off # GPIO 5 + end + device pnp 2e.a off end # ACPI + device pnp 2e.b on # Hardware monitor + io 0x60 = 0x290 + irq 0x70 = 5 + end + end + end + device pci 1.1 on # SM 0 + chip drivers/generic/generic # DIMM 0-0-0 + device i2c 50 on end + end + chip drivers/generic/generic # DIMM 0-0-1 + device i2c 51 on end + end + chip drivers/generic/generic # DIMM 0-1-0 + device i2c 52 on end + end + chip drivers/generic/generic # DIMM 0-1-1 + device i2c 53 on end + end + chip drivers/generic/generic # DIMM 1-0-0 + device i2c 54 on end + end + chip drivers/generic/generic # DIMM 1-0-1 + device i2c 55 on end + end + chip drivers/generic/generic # DIMM 1-1-0 + device i2c 56 on end + end + chip drivers/generic/generic # DIMM 1-1-1 + device i2c 57 on end + end + end + device pci 1.1 on # SM 1 + # PCI device SMBus address will + # depend on addon PCI device, do + # we need to scan_smbus_bus? + # chip drivers/generic/generic # PCIXA slot 1 + # device i2c 50 on end + # end + # chip drivers/generic/generic # PCIXB slot 1 + # device i2c 51 on end + # end + # chip drivers/generic/generic # PCIXB slot 2 + # device i2c 52 on end + # end + # chip drivers/generic/generic # PCI slot 1 + # device i2c 53 on end + # end + # chip drivers/generic/generic # Master MCP55 PCI-E + # device i2c 54 on end + # end + # chip drivers/generic/generic # Slave MCP55 PCI-E + # device i2c 55 on end + # end + # chip drivers/generic/generic # MAC EEPROM + # device i2c 51 on end + # end + end + device pci 2.0 on end # USB 1.1 + device pci 2.1 on end # USB 2 + device pci 4.0 on end # IDE + device pci 5.0 on end # SATA 0 + device pci 5.1 on end # SATA 1 + device pci 5.2 on end # SATA 2 + device pci 6.1 on end # AZA + device pci 8.0 on end # NIC + device pci 9.0 on end # NIC + register "ide0_enable" = "1" + register "sata0_enable" = "1" + register "sata1_enable" = "1" + # 1: SMBus under 2e.8, 2: SM0 3: SM1 + register "mac_eeprom_smbus" = "3" + register "mac_eeprom_addr" = "0x51" + end + end + device pci 18.0 on end # HT 1.0 + device pci 18.0 on end # HT 2.0 + device pci 18.1 on end + device pci 18.2 on end + device pci 18.3 on end + device pci 18.4 on end + end + end end diff --git a/src/mainboard/pcengines/alix1c/devicetree.cb b/src/mainboard/pcengines/alix1c/devicetree.cb index 20e865ab60..8cb8dd3b03 100644 --- a/src/mainboard/pcengines/alix1c/devicetree.cb +++ b/src/mainboard/pcengines/alix1c/devicetree.cb @@ -1,8 +1,8 @@ chip northbridge/amd/lx - device domain 0 on - device pci 1.0 on end + device domain 0 on + device pci 1.0 on end device pci 1.1 on end - chip southbridge/amd/cs5536 + chip southbridge/amd/cs5536 # IRQ 12 and 1 unmasked, Keyboard and Mouse IRQs. OK # SIRQ Mode = Active(Quiet) mode. Save power.... # Invert mask = IRQ 12 and 1 are active high. Keyboard and Mouse IRQs. OK @@ -25,7 +25,7 @@ chip northbridge/amd/lx register "com2_address" = "0x2F8" register "com2_irq" = "3" register "unwanted_vpci[0]" = "0" # End of list has a zero - device pci f.0 on # ISA Bridge + device pci f.0 on # ISA Bridge chip superio/winbond/w83627hf device pnp 2e.0 off # Floppy io 0x60 = 0x3f0 @@ -69,10 +69,10 @@ chip northbridge/amd/lx end device pci f.1 on end # Flash controller device pci f.2 on end # IDE controller - device pci f.3 on end # Audio - device pci f.4 on end # OHCI + device pci f.3 on end # Audio + device pci f.4 on end # OHCI device pci f.5 on end # EHCI - end + end end # APIC cluster is late CPU init. @@ -81,5 +81,4 @@ chip northbridge/amd/lx device lapic 0 on end end end - end diff --git a/src/mainboard/pcengines/alix2d/devicetree.cb b/src/mainboard/pcengines/alix2d/devicetree.cb index f8368ed7fa..e684a8f1a4 100644 --- a/src/mainboard/pcengines/alix2d/devicetree.cb +++ b/src/mainboard/pcengines/alix2d/devicetree.cb @@ -1,8 +1,8 @@ chip northbridge/amd/lx - device domain 0 on - device pci 1.0 on end + device domain 0 on + device pci 1.0 on end device pci 1.1 on end - chip southbridge/amd/cs5536 + chip southbridge/amd/cs5536 # IRQ 12 and 1 unmasked, Keyboard and Mouse IRQs. OK # SIRQ Mode = Active(Quiet) mode. Save power.... # Invert mask = IRQ 12 and 1 are active high. Keyboard and Mouse IRQs. OK @@ -21,18 +21,18 @@ chip northbridge/amd/lx register "com1_enable" = "1" register "com1_address" = "0x3F8" register "com1_irq" = "4" - register "com2_enable" = "1" # Wired on Alix.2D13 only + register "com2_enable" = "1" # Wired on Alix.2D13 only register "com2_address" = "0x2F8" register "com2_irq" = "3" register "unwanted_vpci[0]" = "0x80000900" # Disable VGA controller (not wired) register "unwanted_vpci[1]" = "0x80007B00" # Disable AC97 controller (not wired) - register "unwanted_vpci[2]" = "0" # End of list has a zero + register "unwanted_vpci[2]" = "0" # End of list has a zero device pci f.0 on end # ISA Bridge device pci f.1 on end # Flash controller device pci f.2 on end # IDE controller device pci f.4 on end # OHCI device pci f.5 on end # EHCI - end + end end # APIC cluster is late CPU init. @@ -41,5 +41,4 @@ chip northbridge/amd/lx device lapic 0 on end end end - end diff --git a/src/mainboard/purism/librem_skl/variants/librem13v2/devicetree.cb b/src/mainboard/purism/librem_skl/variants/librem13v2/devicetree.cb index 18dffcf2b5..08ba50607b 100644 --- a/src/mainboard/purism/librem_skl/variants/librem13v2/devicetree.cb +++ b/src/mainboard/purism/librem_skl/variants/librem13v2/devicetree.cb @@ -64,10 +64,10 @@ chip soc/intel/skylake register "HeciEnabled" = "0" register "SaGv" = "3" register "SerialIrqConfigSirqEnable" = "1" - register "PmConfigSlpS3MinAssert" = "2" # 50ms - register "PmConfigSlpS4MinAssert" = "1" # 1s - register "PmConfigSlpSusMinAssert" = "3" # 500ms - register "PmConfigSlpAMinAssert" = "3" # 2s + register "PmConfigSlpS3MinAssert" = "2" # 50ms + register "PmConfigSlpS4MinAssert" = "1" # 1s + register "PmConfigSlpSusMinAssert" = "3" # 500ms + register "PmConfigSlpAMinAssert" = "3" # 2s register "PmTimerDisabled" = "0" register "pirqa_routing" = "PCH_IRQ11" @@ -211,12 +211,12 @@ chip soc/intel/skylake device pci 1d.2 off end # PCI Express Port 11 device pci 1d.3 off end # PCI Express Port 12 device pci 1f.0 on - chip ec/purism/librem - device pnp 0c09.0 on end - end - chip drivers/pc80/tpm - device pnp 0c31.0 on end - end + chip ec/purism/librem + device pnp 0c09.0 on end + end + chip drivers/pc80/tpm + device pnp 0c31.0 on end + end end # LPC Interface device pci 1f.1 on end # P2SB device pci 1f.2 on end # Power Management Controller diff --git a/src/mainboard/purism/librem_skl/variants/librem15v3/devicetree.cb b/src/mainboard/purism/librem_skl/variants/librem15v3/devicetree.cb index 01445dcb8f..4ba6ccddba 100644 --- a/src/mainboard/purism/librem_skl/variants/librem15v3/devicetree.cb +++ b/src/mainboard/purism/librem_skl/variants/librem15v3/devicetree.cb @@ -64,10 +64,10 @@ chip soc/intel/skylake register "HeciEnabled" = "0" register "SaGv" = "3" register "SerialIrqConfigSirqEnable" = "1" - register "PmConfigSlpS3MinAssert" = "2" # 50ms - register "PmConfigSlpS4MinAssert" = "1" # 1s - register "PmConfigSlpSusMinAssert" = "3" # 500ms - register "PmConfigSlpAMinAssert" = "3" # 2s + register "PmConfigSlpS3MinAssert" = "2" # 50ms + register "PmConfigSlpS4MinAssert" = "1" # 1s + register "PmConfigSlpSusMinAssert" = "3" # 500ms + register "PmConfigSlpAMinAssert" = "3" # 2s register "PmTimerDisabled" = "0" register "pirqa_routing" = "PCH_IRQ11" @@ -218,12 +218,12 @@ chip soc/intel/skylake device pci 1d.2 off end # PCI Express Port 11 device pci 1d.3 off end # PCI Express Port 12 device pci 1f.0 on - chip ec/purism/librem - device pnp 0c09.0 on end - end - chip drivers/pc80/tpm - device pnp 0c31.0 on end - end + chip ec/purism/librem + device pnp 0c09.0 on end + end + chip drivers/pc80/tpm + device pnp 0c31.0 on end + end end # LPC Interface device pci 1f.1 on end # P2SB device pci 1f.2 on end # Power Management Controller diff --git a/src/mainboard/roda/rk886ex/acpi/thermal.asl b/src/mainboard/roda/rk886ex/acpi/thermal.asl index 84845becb0..6a4d701988 100644 --- a/src/mainboard/roda/rk886ex/acpi/thermal.asl +++ b/src/mainboard/roda/rk886ex/acpi/thermal.asl @@ -37,7 +37,7 @@ Scope (\_TZ) // Method (_AC1, 0, Serialized) // { - // Return (0xf5c) + // Return (0xf5c) // } // Critical shutdown temperature diff --git a/src/mainboard/roda/rk886ex/devicetree.cb b/src/mainboard/roda/rk886ex/devicetree.cb index 28f8f434c1..bb057f15c3 100644 --- a/src/mainboard/roda/rk886ex/devicetree.cb +++ b/src/mainboard/roda/rk886ex/devicetree.cb @@ -19,23 +19,23 @@ chip northbridge/intel/i945 register "gfx.ndid" = "3" register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }" - device cpu_cluster 0 on - chip cpu/intel/socket_mFCPGA478 - device lapic 0 on end - end - end + device cpu_cluster 0 on + chip cpu/intel/socket_mFCPGA478 + device lapic 0 on end + end + end register "pci_mmio_size" = "768" - device domain 0 on - subsystemid 0x4352 0x6886 inherit - device pci 00.0 on end # host bridge + device domain 0 on + subsystemid 0x4352 0x6886 inherit + device pci 00.0 on end # host bridge # auto detection: #device pci 01.0 off end # i945 PCIe root port device pci 02.0 on end # vga controller device pci 02.1 on end # display controller - chip southbridge/intel/i82801gx + chip southbridge/intel/i82801gx register "pirqa_routing" = "0x0b" register "pirqb_routing" = "0x0b" register "pirqc_routing" = "0x0b" @@ -58,26 +58,26 @@ chip northbridge/intel/i945 register "docking_supported" = "1" register "p_cnt_throttling_supported" = "1" - register "ide_legacy_combined" = "0x1" - register "ide_enable_primary" = "0x1" - register "ide_enable_secondary" = "0x0" - register "sata_ahci" = "0x0" + register "ide_legacy_combined" = "0x1" + register "ide_enable_primary" = "0x1" + register "ide_enable_secondary" = "0x0" + register "sata_ahci" = "0x0" - device pci 1b.0 on end # High Definition Audio - device pci 1c.0 on end # PCIe - device pci 1c.1 on end # PCIe - device pci 1c.2 on end # PCIe + device pci 1b.0 on end # High Definition Audio + device pci 1c.0 on end # PCIe + device pci 1c.1 on end # PCIe + device pci 1c.2 on end # PCIe #device pci 1c.3 off end # PCIe port 4 #device pci 1c.4 off end # PCIe port 5 #device pci 1c.5 off end # PCIe port 6 - device pci 1d.0 on end # USB UHCI - device pci 1d.1 on end # USB UHCI - device pci 1d.2 on end # USB UHCI - device pci 1d.3 on end # USB UHCI - device pci 1d.7 on end # USB2 EHCI - device pci 1e.0 on + device pci 1d.0 on end # USB UHCI + device pci 1d.1 on end # USB UHCI + device pci 1d.2 on end # USB UHCI + device pci 1d.3 on end # USB UHCI + device pci 1d.7 on end # USB2 EHCI + device pci 1e.0 on chip southbridge/ti/pci7420 - register "smartcard_enabled" = "0x0" + register "smartcard_enabled" = "0x0" device pci 3.0 on end device pci 3.1 on end device pci 3.2 on end @@ -86,19 +86,19 @@ chip northbridge/intel/i945 end # PCI bridge #device pci 1e.2 off end # AC'97 Audio #device pci 1e.3 off end # AC'97 Modem - device pci 1f.0 on # LPC bridge - chip superio/smsc/lpc47n227 + device pci 1f.0 on # LPC bridge + chip superio/smsc/lpc47n227 device pnp 2e.1 on # Parallel port io 0x60 = 0x378 irq 0x70 = 5 end device pnp 2e.2 on # COM1 - io 0x60 = 0x3f8 - irq 0x70 = 4 + io 0x60 = 0x3f8 + irq 0x70 = 4 end device pnp 2e.3 on # COM2 - io 0x60 = 0x2f8 - irq 0x70 = 3 + io 0x60 = 0x2f8 + irq 0x70 = 3 end device pnp 2e.5 off # Keyboard+Mouse # io 0x60 = 0x60 @@ -106,7 +106,7 @@ chip northbridge/intel/i945 # irq 0x70 = 1 # irq 0x72 = 12 end - end + end chip superio/renesas/m3885x device pnp ff.1 on # dummy address end @@ -114,11 +114,11 @@ chip northbridge/intel/i945 chip ec/acpi end - end + end #device pci 1f.1 off end # IDE - device pci 1f.2 on end # SATA - device pci 1f.3 on end # SMBus + device pci 1f.2 on end # SATA + device pci 1f.3 on end # SMBus #device pci 1f.4 off end # Realtek ID Codec - end - end + end + end end diff --git a/src/mainboard/roda/rv11/variants/rw11/devicetree.cb b/src/mainboard/roda/rv11/variants/rw11/devicetree.cb index d5f744e98f..b51c86efe2 100644 --- a/src/mainboard/roda/rv11/variants/rw11/devicetree.cb +++ b/src/mainboard/roda/rv11/variants/rw11/devicetree.cb @@ -115,7 +115,7 @@ chip northbridge/intel/sandybridge chip superio/ite/it8783ef register "TMPIN1.mode" = "THERMAL_RESISTOR" register "TMPIN2.mode" = "THERMAL_RESISTOR" - register "ec.vin_mask" = "VIN_ALL" + register "ec.vin_mask" = "VIN_ALL" register "FAN1.mode" = "FAN_SMART_AUTOMATIC" register "FAN1.smart.tmpin" = " 1" register "FAN1.smart.tmp_off" = "60" diff --git a/src/mainboard/supermicro/h8dmr_fam10/devicetree.cb b/src/mainboard/supermicro/h8dmr_fam10/devicetree.cb index 9e52d07f56..ee88c31a97 100644 --- a/src/mainboard/supermicro/h8dmr_fam10/devicetree.cb +++ b/src/mainboard/supermicro/h8dmr_fam10/devicetree.cb @@ -1,152 +1,152 @@ chip northbridge/amd/amdfam10/root_complex # Root complex - device cpu_cluster 0 on # (L)APIC cluster - chip cpu/amd/socket_F_1207 # CPU socket - device lapic 0 on end # Local APIC of the CPU - end - end - device domain 0 on # PCI domain - subsystemid 0x15d9 0x1511 inherit - chip northbridge/amd/amdfam10 # Northbridge / RAM controller - device pci 18.0 on end - device pci 18.0 on end - device pci 18.0 on # SB on link 2.0 - chip southbridge/nvidia/mcp55 # Southbridge - device pci 0.0 on end # HT - device pci 1.0 on # LPC - chip superio/winbond/w83627hf # Super I/O - device pnp 2e.0 off # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 2e.1 off # Parallel port - io 0x60 = 0x378 - irq 0x70 = 7 - end - device pnp 2e.2 on # Com1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.3 on # Com2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.5 on # PS/2 keyboard - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - irq 0x72 = 12 - end - device pnp 2e.6 off # SFI - io 0x62 = 0x100 - end - device pnp 2e.7 off # GPIO, game port, MIDI - io 0x60 = 0x220 - io 0x62 = 0x300 - irq 0x70 = 9 - end - device pnp 2e.8 off end # WDTO PLED - device pnp 2e.9 off end # GPIO SUSLED - device pnp 2e.a off end # ACPI - device pnp 2e.b on # Hardware monitor - io 0x60 = 0x290 - irq 0x70 = 5 - end - end - end - device pci 1.1 on # SM 0 - chip drivers/generic/generic # DIMM 0-0-0 - device i2c 50 on end - end - chip drivers/generic/generic # DIMM 0-0-1 - device i2c 51 on end - end - chip drivers/generic/generic # DIMM 0-1-0 - device i2c 52 on end - end - chip drivers/generic/generic # DIMM 0-1-1 - device i2c 53 on end - end - chip drivers/generic/generic # DIMM 1-0-0 - device i2c 54 on end - end - chip drivers/generic/generic # DIMM 1-0-1 - device i2c 55 on end - end - chip drivers/generic/generic # DIMM 1-1-0 - device i2c 56 on end - end - chip drivers/generic/generic # DIMM 1-1-1 - device i2c 57 on end - end - end - device pci 1.1 on # SM 1 - # PCI device SMBus address will - # depend on addon PCI device, do - # we need to scan_smbus_bus? - # chip drivers/generic/generic # PCIXA slot 1 - # device i2c 50 on end - # end - # chip drivers/generic/generic # PCIXB slot 1 - # device i2c 51 on end - # end - # chip drivers/generic/generic # PCIXB slot 2 - # device i2c 52 on end - # end - # chip drivers/generic/generic # PCI slot 1 - # device i2c 53 on end - # end - # chip drivers/generic/generic # Master MCP55 PCI-E - # device i2c 54 on end - # end - # chip drivers/generic/generic # Slave MCP55 PCI-E - # device i2c 55 on end - # end - chip drivers/generic/generic # MAC EEPROM - device i2c 51 on end - end - end - device pci 2.0 on end # USB 1.1 - device pci 2.1 on end # USB 2 - device pci 4.0 on end # IDE - device pci 5.0 on end # SATA 0 - device pci 5.1 on end # SATA 1 - device pci 5.2 on end # SATA 2 - device pci 6.0 on # PCI - device pci 6.0 on end - end - device pci 6.1 on end # AZA - device pci 8.0 on end # NIC - device pci 9.0 on end # NIC - device pci a.0 on # PCI E 5 - device pci 0.0 on end # NEC PCI-X - device pci 0.1 on # NEC PCI-X - device pci 4.0 on end # SCSI - device pci 4.1 on end # SCSI - end - end - device pci b.0 on end # PCI E 4 - device pci c.0 on end # PCI E 3 - device pci d.0 on end # PCI E 2 - device pci e.0 on end # PCI E 1 - device pci f.0 on end # PCI E 0 - register "ide0_enable" = "1" - register "sata0_enable" = "1" - register "sata1_enable" = "1" - # 1: SMBus under 2e.8, 2: SM0 3: SM1 - register "mac_eeprom_smbus" = "3" - register "mac_eeprom_addr" = "0x51" - end - end - device pci 18.1 on end - device pci 18.2 on end - device pci 18.3 on end - device pci 18.4 on end - device pci 19.0 on end - device pci 19.1 on end - device pci 19.2 on end - device pci 19.3 on end - device pci 19.4 on end - end - end + device cpu_cluster 0 on # (L)APIC cluster + chip cpu/amd/socket_F_1207 # CPU socket + device lapic 0 on end # Local APIC of the CPU + end + end + device domain 0 on # PCI domain + subsystemid 0x15d9 0x1511 inherit + chip northbridge/amd/amdfam10 # Northbridge / RAM controller + device pci 18.0 on end + device pci 18.0 on end + device pci 18.0 on # SB on link 2.0 + chip southbridge/nvidia/mcp55 # Southbridge + device pci 0.0 on end # HT + device pci 1.0 on # LPC + chip superio/winbond/w83627hf # Super I/O + device pnp 2e.0 off # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 2e.1 off # Parallel port + io 0x60 = 0x378 + irq 0x70 = 7 + end + device pnp 2e.2 on # Com1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.3 on # Com2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.5 on # PS/2 keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + irq 0x72 = 12 + end + device pnp 2e.6 off # SFI + io 0x62 = 0x100 + end + device pnp 2e.7 off # GPIO, game port, MIDI + io 0x60 = 0x220 + io 0x62 = 0x300 + irq 0x70 = 9 + end + device pnp 2e.8 off end # WDTO PLED + device pnp 2e.9 off end # GPIO SUSLED + device pnp 2e.a off end # ACPI + device pnp 2e.b on # Hardware monitor + io 0x60 = 0x290 + irq 0x70 = 5 + end + end + end + device pci 1.1 on # SM 0 + chip drivers/generic/generic # DIMM 0-0-0 + device i2c 50 on end + end + chip drivers/generic/generic # DIMM 0-0-1 + device i2c 51 on end + end + chip drivers/generic/generic # DIMM 0-1-0 + device i2c 52 on end + end + chip drivers/generic/generic # DIMM 0-1-1 + device i2c 53 on end + end + chip drivers/generic/generic # DIMM 1-0-0 + device i2c 54 on end + end + chip drivers/generic/generic # DIMM 1-0-1 + device i2c 55 on end + end + chip drivers/generic/generic # DIMM 1-1-0 + device i2c 56 on end + end + chip drivers/generic/generic # DIMM 1-1-1 + device i2c 57 on end + end + end + device pci 1.1 on # SM 1 + # PCI device SMBus address will + # depend on addon PCI device, do + # we need to scan_smbus_bus? + # chip drivers/generic/generic # PCIXA slot 1 + # device i2c 50 on end + # end + # chip drivers/generic/generic # PCIXB slot 1 + # device i2c 51 on end + # end + # chip drivers/generic/generic # PCIXB slot 2 + # device i2c 52 on end + # end + # chip drivers/generic/generic # PCI slot 1 + # device i2c 53 on end + # end + # chip drivers/generic/generic # Master MCP55 PCI-E + # device i2c 54 on end + # end + # chip drivers/generic/generic # Slave MCP55 PCI-E + # device i2c 55 on end + # end + chip drivers/generic/generic # MAC EEPROM + device i2c 51 on end + end + end + device pci 2.0 on end # USB 1.1 + device pci 2.1 on end # USB 2 + device pci 4.0 on end # IDE + device pci 5.0 on end # SATA 0 + device pci 5.1 on end # SATA 1 + device pci 5.2 on end # SATA 2 + device pci 6.0 on # PCI + device pci 6.0 on end + end + device pci 6.1 on end # AZA + device pci 8.0 on end # NIC + device pci 9.0 on end # NIC + device pci a.0 on # PCI E 5 + device pci 0.0 on end # NEC PCI-X + device pci 0.1 on # NEC PCI-X + device pci 4.0 on end # SCSI + device pci 4.1 on end # SCSI + end + end + device pci b.0 on end # PCI E 4 + device pci c.0 on end # PCI E 3 + device pci d.0 on end # PCI E 2 + device pci e.0 on end # PCI E 1 + device pci f.0 on end # PCI E 0 + register "ide0_enable" = "1" + register "sata0_enable" = "1" + register "sata1_enable" = "1" + # 1: SMBus under 2e.8, 2: SM0 3: SM1 + register "mac_eeprom_smbus" = "3" + register "mac_eeprom_addr" = "0x51" + end + end + device pci 18.1 on end + device pci 18.2 on end + device pci 18.3 on end + device pci 18.4 on end + device pci 19.0 on end + device pci 19.1 on end + device pci 19.2 on end + device pci 19.3 on end + device pci 19.4 on end + end + end end diff --git a/src/mainboard/supermicro/h8qme_fam10/devicetree.cb b/src/mainboard/supermicro/h8qme_fam10/devicetree.cb index 6956b45f7e..317d643d9a 100644 --- a/src/mainboard/supermicro/h8qme_fam10/devicetree.cb +++ b/src/mainboard/supermicro/h8qme_fam10/devicetree.cb @@ -1,115 +1,115 @@ chip northbridge/amd/amdfam10/root_complex # Root complex - device cpu_cluster 0 on # (L)APIC cluster - chip cpu/amd/socket_F_1207 # CPU socket - device lapic 0 on end # Local APIC of the CPU - end - end - device domain 0 on # PCI domain - subsystemid 0x15d9 0x1511 inherit - chip northbridge/amd/amdfam10 # Northbridge / RAM controller - device pci 18.0 on end - device pci 18.0 on end - device pci 18.0 on # SB on link 2 - chip southbridge/nvidia/mcp55 # Southbridge - device pci 0.0 on end # HT - device pci 1.0 on # LPC - chip superio/winbond/w83627hf # Super I/O - device pnp 2e.0 off # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 2e.1 off # Parallel port - io 0x60 = 0x378 - irq 0x70 = 7 - end - device pnp 2e.2 on # Com1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.3 off # Com2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.5 on # PS/2 keyboard - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - irq 0x72 = 12 - end - device pnp 2e.6 off # SFI - io 0x62 = 0x100 - end - device pnp 2e.7 off # GPIO, game port, MIDI - io 0x60 = 0x220 - io 0x62 = 0x300 - irq 0x70 = 9 - end - device pnp 2e.8 off end # WDTO PLED - device pnp 2e.9 off end # GPIO SUSLED - device pnp 2e.a off end # ACPI - device pnp 2e.b on # Hardware monitor - io 0x60 = 0x290 - irq 0x70 = 5 - end - end - end - device pci 1.1 on end - device pci 1.1 on # SM 1 - # PCI device SMBus address will - # depend on addon PCI device, do - # we need to scan_smbus_bus? - chip drivers/generic/generic # MAC EEPROM - device i2c 51 on end - end - end - device pci 2.0 on end # USB 1.1 - device pci 2.1 on end # USB 2 - device pci 4.0 on end # IDE - device pci 5.0 on end # SATA 0 - device pci 5.1 on end # SATA 1 - device pci 5.2 on end # SATA 2 - device pci 6.1 off end # AZA - device pci 7.0 on - device pci 1.0 on end - end - device pci 8.0 off end - device pci 9.0 off end - device pci a.0 on end # PCI E 5 - device pci b.0 on end # PCI E 4 - device pci c.0 on end # PCI E 3 - device pci d.0 on end # PCI E 2 - device pci e.0 on end # PCI E 1 - device pci f.0 on end # PCI E 0 - register "ide0_enable" = "1" - register "sata0_enable" = "1" - register "sata1_enable" = "1" - # 1: SMBus under 2e.8, 2: SM0 3: SM1 - register "mac_eeprom_smbus" = "3" - register "mac_eeprom_addr" = "0x51" - end - end - device pci 18.1 on end - device pci 18.2 on end - device pci 18.3 on end - device pci 18.4 on end - device pci 19.0 on end - device pci 19.0 on end - device pci 19.0 on - chip southbridge/amd/amd8132 - device pci 0.0 on end - device pci 0.1 on end - device pci 1.0 on - device pci 3.0 on end - device pci 3.1 on end - end - device pci 1.1 on end - end - end - device pci 19.1 on end - device pci 19.2 on end - device pci 19.3 on end - device pci 19.4 on end - end - end + device cpu_cluster 0 on # (L)APIC cluster + chip cpu/amd/socket_F_1207 # CPU socket + device lapic 0 on end # Local APIC of the CPU + end + end + device domain 0 on # PCI domain + subsystemid 0x15d9 0x1511 inherit + chip northbridge/amd/amdfam10 # Northbridge / RAM controller + device pci 18.0 on end + device pci 18.0 on end + device pci 18.0 on # SB on link 2 + chip southbridge/nvidia/mcp55 # Southbridge + device pci 0.0 on end # HT + device pci 1.0 on # LPC + chip superio/winbond/w83627hf # Super I/O + device pnp 2e.0 off # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 2e.1 off # Parallel port + io 0x60 = 0x378 + irq 0x70 = 7 + end + device pnp 2e.2 on # Com1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.3 off # Com2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.5 on # PS/2 keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + irq 0x72 = 12 + end + device pnp 2e.6 off # SFI + io 0x62 = 0x100 + end + device pnp 2e.7 off # GPIO, game port, MIDI + io 0x60 = 0x220 + io 0x62 = 0x300 + irq 0x70 = 9 + end + device pnp 2e.8 off end # WDTO PLED + device pnp 2e.9 off end # GPIO SUSLED + device pnp 2e.a off end # ACPI + device pnp 2e.b on # Hardware monitor + io 0x60 = 0x290 + irq 0x70 = 5 + end + end + end + device pci 1.1 on end + device pci 1.1 on # SM 1 + # PCI device SMBus address will + # depend on addon PCI device, do + # we need to scan_smbus_bus? + chip drivers/generic/generic # MAC EEPROM + device i2c 51 on end + end + end + device pci 2.0 on end # USB 1.1 + device pci 2.1 on end # USB 2 + device pci 4.0 on end # IDE + device pci 5.0 on end # SATA 0 + device pci 5.1 on end # SATA 1 + device pci 5.2 on end # SATA 2 + device pci 6.1 off end # AZA + device pci 7.0 on + device pci 1.0 on end + end + device pci 8.0 off end + device pci 9.0 off end + device pci a.0 on end # PCI E 5 + device pci b.0 on end # PCI E 4 + device pci c.0 on end # PCI E 3 + device pci d.0 on end # PCI E 2 + device pci e.0 on end # PCI E 1 + device pci f.0 on end # PCI E 0 + register "ide0_enable" = "1" + register "sata0_enable" = "1" + register "sata1_enable" = "1" + # 1: SMBus under 2e.8, 2: SM0 3: SM1 + register "mac_eeprom_smbus" = "3" + register "mac_eeprom_addr" = "0x51" + end + end + device pci 18.1 on end + device pci 18.2 on end + device pci 18.3 on end + device pci 18.4 on end + device pci 19.0 on end + device pci 19.0 on end + device pci 19.0 on + chip southbridge/amd/amd8132 + device pci 0.0 on end + device pci 0.1 on end + device pci 1.0 on + device pci 3.0 on end + device pci 3.1 on end + end + device pci 1.1 on end + end + end + device pci 19.1 on end + device pci 19.2 on end + device pci 19.3 on end + device pci 19.4 on end + end + end end diff --git a/src/mainboard/tyan/s2912_fam10/devicetree.cb b/src/mainboard/tyan/s2912_fam10/devicetree.cb index 485c7e0ef9..e49e16b94e 100644 --- a/src/mainboard/tyan/s2912_fam10/devicetree.cb +++ b/src/mainboard/tyan/s2912_fam10/devicetree.cb @@ -1,141 +1,141 @@ chip northbridge/amd/amdfam10/root_complex # Root complex - device cpu_cluster 0 on # (L)APIC cluster - chip cpu/amd/socket_F_1207 # CPU socket - device lapic 0 on end # Local APIC of the CPU - end - end - device domain 0 on # PCI domain - subsystemid 0x10f1 0x2912 inherit - chip northbridge/amd/amdfam10 # Northbridge / RAM controller - device pci 18.0 on end - device pci 18.0 on end - device pci 18.0 on # SB on link 2 - chip southbridge/nvidia/mcp55 # Southbridge - device pci 0.0 on end # HT - device pci 1.0 on # LPC - chip superio/winbond/w83627hf # Super I/O - device pnp 2e.0 off # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 2e.1 off # Parallel port - io 0x60 = 0x378 - irq 0x70 = 7 - end - device pnp 2e.2 on # Com1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.3 on # Com2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.5 on # PS/2 keyboard - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - irq 0x72 = 12 - end - device pnp 2e.6 off # SFI - io 0x62 = 0x100 - end - device pnp 2e.7 off # GPIO, game port, MIDI - io 0x60 = 0x220 - io 0x62 = 0x300 - irq 0x70 = 9 - end - device pnp 2e.8 off end # WDTO PLED - device pnp 2e.9 off end # GPIO SUSLED - device pnp 2e.a off end # ACPI - device pnp 2e.b on # Hardware monitor - io 0x60 = 0x290 - irq 0x70 = 5 - end - end - end - device pci 1.1 on # SM 0 - chip drivers/generic/generic # DIMM 0-0-0 - device i2c 50 on end - end - chip drivers/generic/generic # DIMM 0-0-1 - device i2c 51 on end - end - chip drivers/generic/generic # DIMM 0-1-0 - device i2c 52 on end - end - chip drivers/generic/generic # DIMM 0-1-1 - device i2c 53 on end - end - chip drivers/generic/generic # DIMM 1-0-0 - device i2c 54 on end - end - chip drivers/generic/generic # DIMM 1-0-1 - device i2c 55 on end - end - chip drivers/generic/generic # DIMM 1-1-0 - device i2c 56 on end - end - chip drivers/generic/generic # DIMM 1-1-1 - device i2c 57 on end - end - end - device pci 1.1 on # SM 1 - # PCI device SMBus address will - # depend on addon PCI device, do - # we need to scan_smbus_bus? - # chip drivers/generic/generic # PCIXA slot 1 - # device i2c 50 on end - # end - # chip drivers/generic/generic # PCIXB slot 1 - # device i2c 51 on end - # end - # chip drivers/generic/generic # PCIXB slot 2 - # device i2c 52 on end - # end - # chip drivers/generic/generic # PCI slot 1 - # device i2c 53 on end - # end - # chip drivers/generic/generic # Master MCP55 PCI-E - # device i2c 54 on end - # end - # chip drivers/generic/generic # Slave MCP55 PCI-E - # device i2c 55 on end - # end - chip drivers/generic/generic # MAC EEPROM - device i2c 51 on end - end - end - device pci 2.0 on end # USB 1.1 - device pci 2.1 on end # USB 2 - device pci 4.0 on end # IDE - device pci 5.0 on end # SATA 0 - device pci 5.1 on end # SATA 1 - device pci 5.2 on end # SATA 2 - device pci 6.0 on # PCI - device pci 4.0 on end - end - device pci 6.1 off end # AZA - device pci 8.0 on end # NIC - device pci 9.0 on end # NIC - device pci a.0 on end # PCI E 5 - device pci b.0 off end # PCI E 4 - device pci c.0 off end # PCI E 3 - device pci d.0 on end # PCI E 2 - device pci e.0 off end # PCI E 1 - device pci f.0 on end # PCI E 0 - register "ide0_enable" = "1" - register "sata0_enable" = "1" - register "sata1_enable" = "1" - # 1: SMBus under 2e.8, 2: SM0 3: SM1 - register "mac_eeprom_smbus" = "3" - register "mac_eeprom_addr" = "0x51" - end - end - device pci 18.1 on end - device pci 18.2 on end - device pci 18.3 on end - device pci 18.4 on end - end - end + device cpu_cluster 0 on # (L)APIC cluster + chip cpu/amd/socket_F_1207 # CPU socket + device lapic 0 on end # Local APIC of the CPU + end + end + device domain 0 on # PCI domain + subsystemid 0x10f1 0x2912 inherit + chip northbridge/amd/amdfam10 # Northbridge / RAM controller + device pci 18.0 on end + device pci 18.0 on end + device pci 18.0 on # SB on link 2 + chip southbridge/nvidia/mcp55 # Southbridge + device pci 0.0 on end # HT + device pci 1.0 on # LPC + chip superio/winbond/w83627hf # Super I/O + device pnp 2e.0 off # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 2e.1 off # Parallel port + io 0x60 = 0x378 + irq 0x70 = 7 + end + device pnp 2e.2 on # Com1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.3 on # Com2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.5 on # PS/2 keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + irq 0x72 = 12 + end + device pnp 2e.6 off # SFI + io 0x62 = 0x100 + end + device pnp 2e.7 off # GPIO, game port, MIDI + io 0x60 = 0x220 + io 0x62 = 0x300 + irq 0x70 = 9 + end + device pnp 2e.8 off end # WDTO PLED + device pnp 2e.9 off end # GPIO SUSLED + device pnp 2e.a off end # ACPI + device pnp 2e.b on # Hardware monitor + io 0x60 = 0x290 + irq 0x70 = 5 + end + end + end + device pci 1.1 on # SM 0 + chip drivers/generic/generic # DIMM 0-0-0 + device i2c 50 on end + end + chip drivers/generic/generic # DIMM 0-0-1 + device i2c 51 on end + end + chip drivers/generic/generic # DIMM 0-1-0 + device i2c 52 on end + end + chip drivers/generic/generic # DIMM 0-1-1 + device i2c 53 on end + end + chip drivers/generic/generic # DIMM 1-0-0 + device i2c 54 on end + end + chip drivers/generic/generic # DIMM 1-0-1 + device i2c 55 on end + end + chip drivers/generic/generic # DIMM 1-1-0 + device i2c 56 on end + end + chip drivers/generic/generic # DIMM 1-1-1 + device i2c 57 on end + end + end + device pci 1.1 on # SM 1 + # PCI device SMBus address will + # depend on addon PCI device, do + # we need to scan_smbus_bus? + # chip drivers/generic/generic # PCIXA slot 1 + # device i2c 50 on end + # end + # chip drivers/generic/generic # PCIXB slot 1 + # device i2c 51 on end + # end + # chip drivers/generic/generic # PCIXB slot 2 + # device i2c 52 on end + # end + # chip drivers/generic/generic # PCI slot 1 + # device i2c 53 on end + # end + # chip drivers/generic/generic # Master MCP55 PCI-E + # device i2c 54 on end + # end + # chip drivers/generic/generic # Slave MCP55 PCI-E + # device i2c 55 on end + # end + chip drivers/generic/generic # MAC EEPROM + device i2c 51 on end + end + end + device pci 2.0 on end # USB 1.1 + device pci 2.1 on end # USB 2 + device pci 4.0 on end # IDE + device pci 5.0 on end # SATA 0 + device pci 5.1 on end # SATA 1 + device pci 5.2 on end # SATA 2 + device pci 6.0 on # PCI + device pci 4.0 on end + end + device pci 6.1 off end # AZA + device pci 8.0 on end # NIC + device pci 9.0 on end # NIC + device pci a.0 on end # PCI E 5 + device pci b.0 off end # PCI E 4 + device pci c.0 off end # PCI E 3 + device pci d.0 on end # PCI E 2 + device pci e.0 off end # PCI E 1 + device pci f.0 on end # PCI E 0 + register "ide0_enable" = "1" + register "sata0_enable" = "1" + register "sata1_enable" = "1" + # 1: SMBus under 2e.8, 2: SM0 3: SM1 + register "mac_eeprom_smbus" = "3" + register "mac_eeprom_addr" = "0x51" + end + end + device pci 18.1 on end + device pci 18.2 on end + device pci 18.3 on end + device pci 18.4 on end + end + end end diff --git a/src/mainboard/tyan/s2912_fam10/resourcemap.c b/src/mainboard/tyan/s2912_fam10/resourcemap.c index 14e3c537f7..bc03d21248 100644 --- a/src/mainboard/tyan/s2912_fam10/resourcemap.c +++ b/src/mainboard/tyan/s2912_fam10/resourcemap.c @@ -266,7 +266,7 @@ static void setup_mb_resource_map(void) * This field defines the highest bus number in configuration region i */ // PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE0), 0x0000FC88, 0x3f000003, /* link 0 of CPU 0 --> Nvidia MCP55 Pro */ -// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE4), 0x0000FC88, 0x7f400203, /* link 2 of CPU 0 --> nvidia io55 */ +// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE4), 0x0000FC88, 0x7f400203, /* link 2 of CPU 0 --> nvidia io55 */ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE8), 0x0000FC88, 0x00000000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xEC), 0x0000FC88, 0x00000000, |