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| author | Tom Warren <twarren@nvidia.com> | 2014-11-17 16:09:38 -0700 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2015-04-10 20:44:24 +0200 |
| commit | bcea3f64a3fd12f8c068e55108ef3e9a9d46acae (patch) | |
| tree | 56e6f68fe89be49796f6de5bbc9a7c80c7f4de9a /src/mainboard | |
| parent | 93147b5ed1b2b7d48dcc47d144b8d11a0f25eba2 (diff) | |
| download | coreboot-bcea3f64a3fd12f8c068e55108ef3e9a9d46acae.tar.xz | |
google/rush_ryu: audio: Setup clocks for AHUB, I2S1, codec, etc.
The Ryu RT5677 audio codec uses EXTPERIPH1 clock (12MHz)
for MCLK1, I2S1 for input. AHUB needs all of its child
peripherals taken out of reset and enabled, too.
This just sets up the audio clocks. More work still to
be done in the codec driver, and some kind of stub needs
to be created/hacked to set up the AD4567 speaker amp
regs for mono output on P1.
BUG=chrome-os-partner:32582
BRANCH=none
TEST=Dumped clock regs and saw correct values
Change-Id: Ifb6551f1e09b38f440f3bb7c759b5e6c0b9e4e44
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 48f989a0291044f5fb4340cc89546325d819d82f
Original-Change-Id: I6c9e760ac39def92a6054d673f781facdbfd70a2
Original-Signed-off-by: Tom Warren <twarren@nvidia.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/229993
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/9523
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/mainboard')
| -rw-r--r-- | src/mainboard/google/rush_ryu/mainboard.c | 31 |
1 files changed, 29 insertions, 2 deletions
diff --git a/src/mainboard/google/rush_ryu/mainboard.c b/src/mainboard/google/rush_ryu/mainboard.c index 2b71c98038..81c15b47d8 100644 --- a/src/mainboard/google/rush_ryu/mainboard.c +++ b/src/mainboard/google/rush_ryu/mainboard.c @@ -57,8 +57,8 @@ static const struct pad_config mmcpads[] = { static const struct pad_config audio_codec_pads[] = { /* H1 is CODEC_RST_L and R2(ROW2) is AUDIO_ENABLE */ - PAD_CFG_GPIO_OUT1(GPIO_PH1, PINMUX_PULL_DOWN), - PAD_CFG_GPIO_OUT1(KB_ROW2, PINMUX_PULL_DOWN), + PAD_CFG_GPIO_OUT1(GPIO_PH1, PINMUX_PULL_DOWN), + PAD_CFG_GPIO_OUT1(KB_ROW2, PINMUX_PULL_DOWN), }; static const struct funit_cfg funits[] = { @@ -186,6 +186,30 @@ static int configure_display_blocks(void) return 0; } +/* Audio init: clocks and enables/resets */ +static void setup_audio(void) +{ + /* External peripheral 1: audio codec (RT5677) using 12MHz CLK1 */ + clock_configure_source(extperiph1, CLK_M, 12000); + + /* + * We need 1.5MHz for I2S1. So, we use CLK_M. CLK_DIVIDER macro + * returns a divisor (0xe) a little bit off from the ideal value (0xd), + * but it's good enough for beeps. + */ + clock_configure_source(i2s1, CLK_M, 1500); + + clock_external_output(1); /* For external RT5677 audio codec. */ + + /* + * Confirmed by NVIDIA hardware team, we need to take ALL audio devices + * connected to AHUB (AUDIO, APBIF, I2S, DAM, AMX, ADX, SPDIF, AFC) out + * of reset and clock-enabled, otherwise reading AHUB devices (in our + * case, I2S/APBIF/AUDIO<XBAR>) will hang. + */ + clock_enable_audio(); +} + static void mainboard_init(device_t dev) { soc_configure_funits(funits, ARRAY_SIZE(funits)); @@ -193,6 +217,9 @@ static void mainboard_init(device_t dev) /* I2C6 bus (audio, etc.) */ soc_configure_i2c6pad(); i2c_init(I2C6_BUS); + + setup_audio(); + elog_init(); elog_add_boot_reason(); |