sb/intel/ibexpeak: Implement PCH function disable in chip_ops

This does the following:
- implement a PCH disable function that will be called by the PCI
  drivers as part of their chip_ops
- removes the iobp_x calls as those don't exist on ibexpeak
- complete the devicetree with to be disabled PCI devices for the
  chip_ops to be called
- Clean up some code copied from bd82x6x

Change-Id: I78d25ffe9af482c77d397a9fdb4f0127e40baddc
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35753
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>

2 files changed, 30 insertions, 4 deletions

diff --git a/src/mainboard/lenovo/x201/devicetree.cb b/src/mainboard/lenovo/x201/devicetree.cb
index de6d568dd8..3ababc9e9c 100644
--- a/src/mainboard/lenovo/x201/devicetree.cb
+++ b/src/mainboard/lenovo/x201/devicetree.cb
@@ -74,9 +74,10 @@ chip northbridge/intel/nehalem
 
 			register "pcie_hotplug_map" = "{ 0, 0, 0, 1, 0, 0, 0, 0 }"
 
-			device pci 16.2 on # IDE/SATA
-				subsystemid 0x17aa 0x2161
-			end
+			device pci 16.0 on end # Management Engine Interface 1
+			device pci 16.1 off end # Management Engine Interface 2
+			device pci 16.2 off end # Management Engine IDE-R, only management boot
+			device pci 16.3 off end # Management Engine KT
 
 			device pci 19.0 on # Ethernet
 				subsystemid 0x17aa 0x2153
@@ -92,14 +93,19 @@ chip northbridge/intel/nehalem
 
 			device pci 1c.0 on end # PCIe Port #1
 			device pci 1c.1 on end # PCIe Port #2 (wwan)
+			device pci 1c.2 off end
 			device pci 1c.3 on
 				smbios_slot_desc "7" "3" "ExpressCard Slot" "8"
 			end # PCIe Port #4 (Expresscard)
 			device pci 1c.4 on end # PCIe Port #5 (wlan)
+			device pci 1c.5 off end
+			device pci 1c.6 off end
+			device pci 1c.7 off end
 
 			device pci 1d.0 on # USB2 EHCI
 				subsystemid 0x17aa 0x2163
 			end
+			device pci 1e.0 on end # PCI 2 PCI bridge
 			device pci 1f.0 on # PCI-LPC bridge
 				subsystemid 0x17aa 0x2166
 				chip superio/nsc/pc87382
@@ -179,6 +185,9 @@ chip northbridge/intel/nehalem
 					device i2c 5f on end
 				end
 			end
+			device pci 1f.4 off end
+			device pci 1f.5 off end
+			device pci 1f.6 on end
 		end
 	end
 end
diff --git a/src/mainboard/packardbell/ms2290/devicetree.cb b/src/mainboard/packardbell/ms2290/devicetree.cb
index c98f9a36bc..bf1c171222 100644
--- a/src/mainboard/packardbell/ms2290/devicetree.cb
+++ b/src/mainboard/packardbell/ms2290/devicetree.cb
@@ -66,6 +66,13 @@ chip northbridge/intel/nehalem
 			register "alt_gp_smi_en" = "0x0000"
 			register "gen1_dec" = "0x040069"
 
+			device pci 16.0 off end # Management Engine Interface 1
+			device pci 16.1 off end # Management Engine Interface 2
+			device pci 16.2 off end # Management Engine IDE-R, only management boot
+			device pci 16.3 off end # Management Engine KT
+
+			device pci 19.0 off end # Ethernet
+
 			device pci 1a.0 on # USB2 EHCI
 				subsystemid 0x1025 0x0379
 			end
@@ -75,11 +82,18 @@ chip northbridge/intel/nehalem
 			end
 
 			device pci 1c.0 on end # PCIe Port #1
-			device pci 1c.1 on end # PCIe Port #1
+			device pci 1c.1 on end # PCIe Port #2
+			device pci 1c.2 off end
+			device pci 1c.3 off end
+			device pci 1c.4 off end
+			device pci 1c.5 off end
+			device pci 1c.6 off end
+			device pci 1c.7 off end
 
 			device pci 1d.0 on # USB2 EHCI
 				subsystemid 0x1025 0x0379
 			end
+			device pci 1e.0 on end # PCI 2 PCI bridge
 			device pci 1f.0 on # PCI-LPC bridge
 				subsystemid 0x1025 0x0379
 			end
@@ -89,6 +103,9 @@ chip northbridge/intel/nehalem
 			device pci 1f.3 on # SMBUS
 				subsystemid 0x1025 0x0379
 			end
+			device pci 1f.4 off end
+			device pci 1f.5 off end
+			device pci 1f.6 off end
 		end
 	end
 end