diff options
| author | Aaron Durbin <adurbin@chromium.org> | 2015-11-11 16:50:52 -0600 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2015-11-18 16:28:49 +0100 |
| commit | d49d42f629e09a36e9ce498319d5ad2fb4744a32 (patch) | |
| tree | d36996d3f820763141ed8a6ec27fe94699d1ce27 /src/mainboard | |
| parent | ce6c35699b605dd097dd25642c480738b9738222 (diff) | |
| download | coreboot-d49d42f629e09a36e9ce498319d5ad2fb4744a32.tar.xz | |
google/chell: disable power rails in sleep path
For the rails controllable by the host processor through
gpios turn them off in the sleep paths. The result is that
S3 and S5 will turn off those rails.
BUG=chrome-os-partner:47228
BRANCH=None
TEST=Built for chell.
Change-Id: I5843f13be43a6ec143600585a5a0c47563e533dd
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: ddd5860dc0cfee68ec2f77f4931665740bede08c
Original-Change-Id: Ife0e2fb11373dd129e20b914b45cd5b56c3493f7
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/312321
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/12446
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/mainboard')
| -rw-r--r-- | src/mainboard/google/chell/gpio.h | 7 | ||||
| -rw-r--r-- | src/mainboard/google/chell/smihandler.c | 30 |
2 files changed, 34 insertions, 3 deletions
diff --git a/src/mainboard/google/chell/gpio.h b/src/mainboard/google/chell/gpio.h index cb10be4915..20880cdb27 100644 --- a/src/mainboard/google/chell/gpio.h +++ b/src/mainboard/google/chell/gpio.h @@ -49,6 +49,13 @@ #define EC_SCI_GPI GPE0_DW2_16 #define EC_SMI_GPI GPP_E15 +/* Power rail control signals. */ +#define EN_PP3300_KEPLER GPP_C11 +#define EN_PP3300_DX_TOUCH GPP_C22 +#define EN_PP3300_DX_EMMC GPP_D5 +#define EN_PP1800_DX_EMMC GPP_D6 +#define EN_PP3300_DX_CAM GPP_D12 + #ifndef __ACPI__ /* Pad configuration in ramstage. */ static const struct pad_config gpio_table[] = { diff --git a/src/mainboard/google/chell/smihandler.c b/src/mainboard/google/chell/smihandler.c index 7e34712515..cd0cc19a35 100644 --- a/src/mainboard/google/chell/smihandler.c +++ b/src/mainboard/google/chell/smihandler.c @@ -19,6 +19,7 @@ #include <cpu/x86/smm.h> #include <elog.h> #include <ec/google/chromeec/ec.h> +#include <gpio.h> #include <soc/iomap.h> #include <soc/nvs.h> #include <soc/pm.h> @@ -80,9 +81,8 @@ void mainboard_smi_gpi_handler(const struct gpi_status *sts) } } -void mainboard_smi_sleep(u8 slp_typ) +static void google_ec_smi_sleep(u8 slp_typ) { -#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC) switch (slp_typ) { case 3: /* Enable wake events */ @@ -101,7 +101,31 @@ void mainboard_smi_sleep(u8 slp_typ) /* Clear pending events that may trigger immediate wake */ while (google_chromeec_get_event() != 0) ; -#endif +} + +static void mainboard_gpio_smi_sleep(u8 slp_typ) +{ + int i; + + /* Power down the rails on any sleep type. */ + gpio_t active_high_signals[] = { + EN_PP3300_KEPLER, + EN_PP3300_DX_TOUCH, + EN_PP3300_DX_EMMC, + EN_PP1800_DX_EMMC, + EN_PP3300_DX_CAM, + }; + + for (i = 0; i < ARRAY_SIZE(active_high_signals); i++) + gpio_set(active_high_signals[i], 0); +} + +void mainboard_smi_sleep(u8 slp_typ) +{ + if (IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)) + google_ec_smi_sleep(slp_typ); + + mainboard_gpio_smi_sleep(slp_typ); } int mainboard_smi_apmc(u8 apmc) |