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| author | Scott Duplichan <scott@notabs.org> | 2011-05-15 21:51:31 +0000 |
|---|---|---|
| committer | Marc Jones <marc.jones@amd.com> | 2011-05-15 21:51:31 +0000 |
| commit | d9a634c7560d0af50e141ad18ffc8c48519209e7 (patch) | |
| tree | 2ca4b11c1b982b95cdc1b7bdd694fd7f7977d8bc /src/mainboard | |
| parent | e73fc20886e094149f44f9306ef15971154f59ee (diff) | |
| download | coreboot-d9a634c7560d0af50e141ad18ffc8c48519209e7.tar.xz | |
Switch processor cores to pstate 0 early to reduce boot time.
Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Marc Jones <marcj303@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6583 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard')
| -rw-r--r-- | src/mainboard/amd/persimmon/romstage.c | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/mainboard/amd/persimmon/romstage.c b/src/mainboard/amd/persimmon/romstage.c index 51e7a8df1f..e3ed847fdb 100644 --- a/src/mainboard/amd/persimmon/romstage.c +++ b/src/mainboard/amd/persimmon/romstage.c @@ -47,6 +47,9 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) u32 val; u8 reg8; + // all cores: set pstate 0 (1600 MHz) early to save a few ms of boot time + __writemsr (0xc0010062, 0); + // early enable of SPI 33 MHz fast mode read if (boot_cpu()) { |