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| author | Hamish Guthrie <hamish@prodigi.ch> | 2005-08-17 04:48:17 +0000 |
|---|---|---|
| committer | Hamish Guthrie <hamish@prodigi.ch> | 2005-08-17 04:48:17 +0000 |
| commit | e251c42197225d3783699343e0805c425aeae8e9 (patch) | |
| tree | 3544e36115026aae4dfa74cd569497c5e322cd46 /src/mainboard | |
| parent | 3d291aa6a2e5ae309a805c602a3768b6d86d8a2d (diff) | |
| download | coreboot-e251c42197225d3783699343e0805c425aeae8e9.tar.xz | |
Changed udelay in delay_tsc to be more be more considerate of single
processor environments.
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2009 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard')
| -rw-r--r-- | src/mainboard/eaglelion/5bcm/Options.lb | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/src/mainboard/eaglelion/5bcm/Options.lb b/src/mainboard/eaglelion/5bcm/Options.lb index 1c87e9f244..df3d1bdfb6 100644 --- a/src/mainboard/eaglelion/5bcm/Options.lb +++ b/src/mainboard/eaglelion/5bcm/Options.lb @@ -37,6 +37,8 @@ uses CONFIG_CONSOLE_SERIAL8250 uses TTYS0_BAUD uses TTYS0_BASE uses TTYS0_LCS +uses CONFIG_UDELAY_TSC +uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 ## ROM_SIZE is the size of boot ROM that this board will use. default ROM_SIZE = 256*1024 @@ -60,6 +62,11 @@ default HAVE_MP_TABLE=0 ## default HAVE_HARD_RESET=0 +## Delay timer options +## +default CONFIG_UDELAY_TSC=1 +default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1 + ## ## Build code to export a programmable irq routing table ## |