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| author | Aaron Durbin <adurbin@chromium.org> | 2015-09-24 12:26:31 -0500 |
|---|---|---|
| committer | Aaron Durbin <adurbin@gmail.com> | 2015-10-11 23:55:45 +0000 |
| commit | e6af4be1587f34f2f79d6e8b9ece94cfa7cd4c8e (patch) | |
| tree | 94503e1a9526b30ff2356357d4a91a4e89900034 /src/mainboard | |
| parent | cc5ac17fab97bd16f3122bb492fbdc28644c8567 (diff) | |
| download | coreboot-e6af4be1587f34f2f79d6e8b9ece94cfa7cd4c8e.tar.xz | |
intel fsp1_1: prepare for romstage vboot verification split
In order to introduce a verstage which performs vboot
verification the cache-as-ram environment needs to be
generalized and split into pieces that can be utilized
in romstage and/or verstage. Therefore, the romstage
pieces were removed from the cache-as-ram specific pieces
that are generic:
- Add fsp/car.h to house the declarations for functions in
the cache-as-ram environment
- Only have cache_as_ram_params which are isolated form the
cache-as-ram environment aside from FSP_INFO_HEADER.
- Hardware requirements for console initialization is done
in the cache-as-ram specific files.
- Provide after_raminit.S which can be included from a
romstage separated from cache-as-ram as well as one that
is tightly coupled to the cache-as-ram environment.
- Update the fallout from the API changes in
soc/intel/{braswell,common,skylake}.
BUG=chrome-os-partner:44827
BRANCH=None
TEST=Built and booted glados.
Original-Change-Id: I2fb93dfebd7d9213365a8b0e811854fde80c973a
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/302481
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Change-Id: Id93089b7c699dd6d83fed8831a7e275410f05afe
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11816
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/mainboard')
| -rw-r--r-- | src/mainboard/google/cyan/com_init.c | 2 | ||||
| -rwxr-xr-x | src/mainboard/intel/strago/com_init.c | 2 |
2 files changed, 2 insertions, 2 deletions
diff --git a/src/mainboard/google/cyan/com_init.c b/src/mainboard/google/cyan/com_init.c index 00f79dcb87..e94f58500c 100644 --- a/src/mainboard/google/cyan/com_init.c +++ b/src/mainboard/google/cyan/com_init.c @@ -24,7 +24,7 @@ #include <soc/pci_devs.h> #include <soc/romstage.h> -void mainboard_pre_console_init(void) +void car_mainboard_pre_console_init(void) { uint32_t reg; uint32_t *pad_config_reg; diff --git a/src/mainboard/intel/strago/com_init.c b/src/mainboard/intel/strago/com_init.c index d29eed3aab..309a73dee8 100755 --- a/src/mainboard/intel/strago/com_init.c +++ b/src/mainboard/intel/strago/com_init.c @@ -33,7 +33,7 @@ /* family number in high byte and inner pad number in lowest byte */ -void mainboard_pre_console_init(void) +void car_mainboard_pre_console_init(void) { uint32_t reg; uint32_t *pad_config_reg; |