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| author | Patrick Georgi <patrick.georgi@coresystems.de> | 2010-10-01 14:50:12 +0000 |
|---|---|---|
| committer | Patrick Georgi <patrick.georgi@coresystems.de> | 2010-10-01 14:50:12 +0000 |
| commit | e82618d03719e1c3f012b6ac227aa4b34ae4950b (patch) | |
| tree | 8b346ea13157962dc040299579101958b9fe738f /src/mainboard | |
| parent | f11b81d18d36ecf732452a861d79ecd75f380adc (diff) | |
| download | coreboot-e82618d03719e1c3f012b6ac227aa4b34ae4950b.tar.xz | |
Move CACHE_AS_RAM_ADDRESS_DEBUG out of romstage.c into Kconfig,
rename it slightly, make it visible only on relevant northbridges,
drop it entirely from via boards (as they seem to have picked it
up from AMD code without using it themselves), and make it
default to false for all boards.
Some romstages used to set this to "true" (ie. "print debug output"),
but I didn't follow up on it in Kconfig - if you need it to debug CAR,
enable it yourself.
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5898 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard')
26 files changed, 0 insertions, 28 deletions
diff --git a/src/mainboard/amd/mahogany_fam10/romstage.c b/src/mainboard/amd/mahogany_fam10/romstage.c index d7f8cb9c48..6f47f66283 100644 --- a/src/mainboard/amd/mahogany_fam10/romstage.c +++ b/src/mainboard/amd/mahogany_fam10/romstage.c @@ -22,7 +22,6 @@ //#define SYSTEM_TYPE 2 /* MOBILE */ #define RAMINIT_SYSINFO 1 -#define CACHE_AS_RAM_ADDRESS_DEBUG 1 #define SET_NB_CFG_54 1 diff --git a/src/mainboard/amd/serengeti_cheetah/ap_romstage.c b/src/mainboard/amd/serengeti_cheetah/ap_romstage.c index 5a9d7049dd..d8539932b2 100644 --- a/src/mainboard/amd/serengeti_cheetah/ap_romstage.c +++ b/src/mainboard/amd/serengeti_cheetah/ap_romstage.c @@ -2,7 +2,6 @@ #define __PRE_RAM__ #define RAMINIT_SYSINFO 1 -#define CACHE_AS_RAM_ADDRESS_DEBUG 0 #define SET_NB_CFG_54 1 diff --git a/src/mainboard/amd/serengeti_cheetah/romstage.c b/src/mainboard/amd/serengeti_cheetah/romstage.c index 65cabe9a4f..fed8d6a6c3 100644 --- a/src/mainboard/amd/serengeti_cheetah/romstage.c +++ b/src/mainboard/amd/serengeti_cheetah/romstage.c @@ -1,5 +1,4 @@ #define RAMINIT_SYSINFO 1 -#define CACHE_AS_RAM_ADDRESS_DEBUG 0 #define SET_NB_CFG_54 1 diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c b/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c index 742700575b..b0a0f08829 100644 --- a/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c +++ b/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c @@ -22,7 +22,6 @@ //#define SYSTEM_TYPE 2 /* MOBILE */ #define RAMINIT_SYSINFO 1 -#define CACHE_AS_RAM_ADDRESS_DEBUG 1 #define SET_NB_CFG_54 1 diff --git a/src/mainboard/amd/tilapia_fam10/romstage.c b/src/mainboard/amd/tilapia_fam10/romstage.c index 2971a7fc8a..3e190fec9c 100644 --- a/src/mainboard/amd/tilapia_fam10/romstage.c +++ b/src/mainboard/amd/tilapia_fam10/romstage.c @@ -22,7 +22,6 @@ //#define SYSTEM_TYPE 2 /* MOBILE */ #define RAMINIT_SYSINFO 1 -#define CACHE_AS_RAM_ADDRESS_DEBUG 1 #define SET_NB_CFG_54 1 diff --git a/src/mainboard/asus/a8v-e_se/romstage.c b/src/mainboard/asus/a8v-e_se/romstage.c index 1f56947eed..aba667986f 100644 --- a/src/mainboard/asus/a8v-e_se/romstage.c +++ b/src/mainboard/asus/a8v-e_se/romstage.c @@ -24,8 +24,6 @@ #define RAMINIT_SYSINFO 1 -#define CACHE_AS_RAM_ADDRESS_DEBUG 0 - unsigned int get_sbdn(unsigned bus); /* Used by raminit. */ diff --git a/src/mainboard/asus/m2v-mx_se/romstage.c b/src/mainboard/asus/m2v-mx_se/romstage.c index cbf8ef570b..76b3e9db93 100644 --- a/src/mainboard/asus/m2v-mx_se/romstage.c +++ b/src/mainboard/asus/m2v-mx_se/romstage.c @@ -24,8 +24,6 @@ #define RAMINIT_SYSINFO 1 -#define CACHE_AS_RAM_ADDRESS_DEBUG 0 - unsigned int get_sbdn(unsigned bus); /* Used by raminit. */ diff --git a/src/mainboard/asus/m4a785-m/romstage.c b/src/mainboard/asus/m4a785-m/romstage.c index a0725eeb5b..770cee1cbe 100644 --- a/src/mainboard/asus/m4a785-m/romstage.c +++ b/src/mainboard/asus/m4a785-m/romstage.c @@ -22,7 +22,6 @@ //#define SYSTEM_TYPE 2 /* MOBILE */ #define RAMINIT_SYSINFO 1 -#define CACHE_AS_RAM_ADDRESS_DEBUG 1 #define SET_NB_CFG_54 1 diff --git a/src/mainboard/gigabyte/ga_2761gxdk/ap_romstage.c b/src/mainboard/gigabyte/ga_2761gxdk/ap_romstage.c index 7644ab49ba..1ecbd61be4 100644 --- a/src/mainboard/gigabyte/ga_2761gxdk/ap_romstage.c +++ b/src/mainboard/gigabyte/ga_2761gxdk/ap_romstage.c @@ -25,7 +25,6 @@ #define __PRE_RAM__ #define RAMINIT_SYSINFO 1 -#define CACHE_AS_RAM_ADDRESS_DEBUG 0 #define SET_NB_CFG_54 1 diff --git a/src/mainboard/gigabyte/m57sli/ap_romstage.c b/src/mainboard/gigabyte/m57sli/ap_romstage.c index d429b4cd31..0883a5a60f 100644 --- a/src/mainboard/gigabyte/m57sli/ap_romstage.c +++ b/src/mainboard/gigabyte/m57sli/ap_romstage.c @@ -23,7 +23,6 @@ #define __PRE_RAM__ #define RAMINIT_SYSINFO 1 -#define CACHE_AS_RAM_ADDRESS_DEBUG 0 #define SET_NB_CFG_54 1 diff --git a/src/mainboard/gigabyte/ma785gmt/romstage.c b/src/mainboard/gigabyte/ma785gmt/romstage.c index 9e221fc948..13664418ab 100644 --- a/src/mainboard/gigabyte/ma785gmt/romstage.c +++ b/src/mainboard/gigabyte/ma785gmt/romstage.c @@ -22,7 +22,6 @@ //#define SYSTEM_TYPE 2 /* MOBILE */ #define RAMINIT_SYSINFO 1 -#define CACHE_AS_RAM_ADDRESS_DEBUG 1 #define SET_NB_CFG_54 1 diff --git a/src/mainboard/gigabyte/ma78gm/romstage.c b/src/mainboard/gigabyte/ma78gm/romstage.c index 56133accd1..64b560d683 100644 --- a/src/mainboard/gigabyte/ma78gm/romstage.c +++ b/src/mainboard/gigabyte/ma78gm/romstage.c @@ -22,7 +22,6 @@ //#define SYSTEM_TYPE 2 /* MOBILE */ #define RAMINIT_SYSINFO 1 -#define CACHE_AS_RAM_ADDRESS_DEBUG 1 #define SET_NB_CFG_54 1 diff --git a/src/mainboard/iei/kino-780am2-fam10/romstage.c b/src/mainboard/iei/kino-780am2-fam10/romstage.c index 38d94a60d4..e53ddf4251 100644 --- a/src/mainboard/iei/kino-780am2-fam10/romstage.c +++ b/src/mainboard/iei/kino-780am2-fam10/romstage.c @@ -22,7 +22,6 @@ //#define SYSTEM_TYPE 2 /* MOBILE */ #define RAMINIT_SYSINFO 1 -#define CACHE_AS_RAM_ADDRESS_DEBUG 1 #define SET_NB_CFG_54 1 diff --git a/src/mainboard/iwill/dk8_htx/romstage.c b/src/mainboard/iwill/dk8_htx/romstage.c index 1af5c2c55f..8fea9d9abf 100644 --- a/src/mainboard/iwill/dk8_htx/romstage.c +++ b/src/mainboard/iwill/dk8_htx/romstage.c @@ -1,5 +1,4 @@ #define RAMINIT_SYSINFO 1 -#define CACHE_AS_RAM_ADDRESS_DEBUG 0 #define SET_NB_CFG_54 1 diff --git a/src/mainboard/iwill/dk8s2/romstage.c b/src/mainboard/iwill/dk8s2/romstage.c index 706014b9c2..77691a6ce2 100644 --- a/src/mainboard/iwill/dk8s2/romstage.c +++ b/src/mainboard/iwill/dk8s2/romstage.c @@ -1,5 +1,4 @@ #define RAMINIT_SYSINFO 1 -#define CACHE_AS_RAM_ADDRESS_DEBUG 0 #define SET_NB_CFG_54 1 diff --git a/src/mainboard/iwill/dk8x/romstage.c b/src/mainboard/iwill/dk8x/romstage.c index 706014b9c2..77691a6ce2 100644 --- a/src/mainboard/iwill/dk8x/romstage.c +++ b/src/mainboard/iwill/dk8x/romstage.c @@ -1,5 +1,4 @@ #define RAMINIT_SYSINFO 1 -#define CACHE_AS_RAM_ADDRESS_DEBUG 0 #define SET_NB_CFG_54 1 diff --git a/src/mainboard/jetway/pa78vm5/romstage.c b/src/mainboard/jetway/pa78vm5/romstage.c index 24302fe19a..b966c465e8 100644 --- a/src/mainboard/jetway/pa78vm5/romstage.c +++ b/src/mainboard/jetway/pa78vm5/romstage.c @@ -23,7 +23,6 @@ //#define SYSTEM_TYPE 2 /* MOBILE */ #define RAMINIT_SYSINFO 1 -#define CACHE_AS_RAM_ADDRESS_DEBUG 1 #define SET_NB_CFG_54 1 diff --git a/src/mainboard/msi/ms7260/ap_romstage.c b/src/mainboard/msi/ms7260/ap_romstage.c index 5b88a6d989..16b47685a6 100644 --- a/src/mainboard/msi/ms7260/ap_romstage.c +++ b/src/mainboard/msi/ms7260/ap_romstage.c @@ -24,7 +24,6 @@ #define __PRE_RAM__ #define RAMINIT_SYSINFO 1 -#define CACHE_AS_RAM_ADDRESS_DEBUG 0 #define SET_NB_CFG_54 1 /* Used by RAM init. */ #define QRANK_DIMM_SUPPORT 1 #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0 diff --git a/src/mainboard/msi/ms7260/romstage.c b/src/mainboard/msi/ms7260/romstage.c index 908138a5d3..2605a16c3f 100644 --- a/src/mainboard/msi/ms7260/romstage.c +++ b/src/mainboard/msi/ms7260/romstage.c @@ -20,7 +20,6 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -// #define CACHE_AS_RAM_ADDRESS_DEBUG 1 // #define RAM_TIMING_DEBUG 1 // #define DQS_TRAIN_DEBUG 1 // #define RES_DEBUG 1 diff --git a/src/mainboard/msi/ms9185/romstage.c b/src/mainboard/msi/ms9185/romstage.c index a2bf78bf1b..522e2f3e11 100644 --- a/src/mainboard/msi/ms9185/romstage.c +++ b/src/mainboard/msi/ms9185/romstage.c @@ -24,7 +24,6 @@ */ #define RAMINIT_SYSINFO 1 -#define CACHE_AS_RAM_ADDRESS_DEBUG 0 #define SET_NB_CFG_54 1 diff --git a/src/mainboard/msi/ms9282/romstage.c b/src/mainboard/msi/ms9282/romstage.c index ed8ee85647..950f7dca59 100644 --- a/src/mainboard/msi/ms9282/romstage.c +++ b/src/mainboard/msi/ms9282/romstage.c @@ -23,7 +23,6 @@ */ #define RAMINIT_SYSINFO 1 -#define CACHE_AS_RAM_ADDRESS_DEBUG 0 #define SET_NB_CFG_54 1 diff --git a/src/mainboard/nvidia/l1_2pvv/ap_romstage.c b/src/mainboard/nvidia/l1_2pvv/ap_romstage.c index 8d3cb8d9c7..5d6f45e328 100644 --- a/src/mainboard/nvidia/l1_2pvv/ap_romstage.c +++ b/src/mainboard/nvidia/l1_2pvv/ap_romstage.c @@ -23,7 +23,6 @@ #define __PRE_RAM__ #define RAMINIT_SYSINFO 1 -#define CACHE_AS_RAM_ADDRESS_DEBUG 0 #define SET_NB_CFG_54 1 diff --git a/src/mainboard/supermicro/h8dme/ap_romstage.c b/src/mainboard/supermicro/h8dme/ap_romstage.c index 8643bed96f..8e8b73bd2a 100644 --- a/src/mainboard/supermicro/h8dme/ap_romstage.c +++ b/src/mainboard/supermicro/h8dme/ap_romstage.c @@ -23,7 +23,6 @@ #define __PRE_RAM__ #define RAMINIT_SYSINFO 1 -#define CACHE_AS_RAM_ADDRESS_DEBUG 0 #define SET_NB_CFG_54 1 diff --git a/src/mainboard/supermicro/h8dmr/ap_romstage.c b/src/mainboard/supermicro/h8dmr/ap_romstage.c index 8643bed96f..8e8b73bd2a 100644 --- a/src/mainboard/supermicro/h8dmr/ap_romstage.c +++ b/src/mainboard/supermicro/h8dmr/ap_romstage.c @@ -23,7 +23,6 @@ #define __PRE_RAM__ #define RAMINIT_SYSINFO 1 -#define CACHE_AS_RAM_ADDRESS_DEBUG 0 #define SET_NB_CFG_54 1 diff --git a/src/mainboard/tyan/s2912/ap_romstage.c b/src/mainboard/tyan/s2912/ap_romstage.c index 99036d0716..e60992f88a 100644 --- a/src/mainboard/tyan/s2912/ap_romstage.c +++ b/src/mainboard/tyan/s2912/ap_romstage.c @@ -23,7 +23,6 @@ #define __PRE_RAM__ #define RAMINIT_SYSINFO 1 -#define CACHE_AS_RAM_ADDRESS_DEBUG 0 #define SET_NB_CFG_54 1 diff --git a/src/mainboard/via/epia-m700/romstage.c b/src/mainboard/via/epia-m700/romstage.c index abf87a77fc..479305fa2e 100644 --- a/src/mainboard/via/epia-m700/romstage.c +++ b/src/mainboard/via/epia-m700/romstage.c @@ -23,7 +23,6 @@ */ #define RAMINIT_SYSINFO 1 -#define CACHE_AS_RAM_ADDRESS_DEBUG 0 #define PAYLOAD_IS_SEABIOS 0 #include <stdint.h> |