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| author | Furquan Shaikh <furquan@chromium.org> | 2016-11-09 10:35:23 -0800 |
|---|---|---|
| committer | Furquan Shaikh <furquan@google.com> | 2016-11-10 20:40:19 +0100 |
| commit | ee019d016d1f1d61cbba3a4b8bdc897f209981bb (patch) | |
| tree | be19fc9e0a31847d96be7a59c21315b7e2da60e5 /src/mainboard | |
| parent | 73edd2b7c07fb8ad5455086f126c079734a904b7 (diff) | |
| download | coreboot-ee019d016d1f1d61cbba3a4b8bdc897f209981bb.tar.xz | |
mainboard/google/reef: Tune digitizer I2C frequency to 400kHz
This brings the I2C frequency down to 400kHz which is spec for fast
I2C.
BUG=chrome-os-partner:56246
BRANCH=None
TEST=Verified frequency in kernel.
Change-Id: Ib83c57eec8644903cb9c4b2ab50c94038eb690c1
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/17342
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/mainboard')
| -rw-r--r-- | src/mainboard/google/reef/variants/baseboard/devicetree.cb | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/src/mainboard/google/reef/variants/baseboard/devicetree.cb b/src/mainboard/google/reef/variants/baseboard/devicetree.cb index 5aa1d32ec2..6c8cd8f20d 100644 --- a/src/mainboard/google/reef/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/reef/variants/baseboard/devicetree.cb @@ -95,6 +95,17 @@ chip soc/intel/apollolake } }" + # Limit digitizer speed to 400kHz with manually tuned values. + register "i2c[5]" = "{ + .speed = I2C_SPEED_FAST, + .speed_config[0] = { + .speed = I2C_SPEED_FAST, + .scl_lcnt = 0xd0, + .scl_hcnt = 0x68, + .sda_hold = 0x27, + } + }" + # Minimum SLP S3 assertion width 28ms. register "slp_s3_assertion_width_usecs" = "28000" |