hp/abm: Switch away from AGESA_LEGACY

Change-Id: Ie2f1eb5a101b9c392a7bd5cb2338dd6a6fdcfe52
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/20721
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>

5 files changed, 45 insertions, 130 deletions

diff --git a/src/mainboard/hp/abm/BiosCallOuts.c b/src/mainboard/hp/abm/BiosCallOuts.c
index 70573be257..729753dd8b 100644
--- a/src/mainboard/hp/abm/BiosCallOuts.c
+++ b/src/mainboard/hp/abm/BiosCallOuts.c
@@ -17,14 +17,13 @@
 #include "AGESA.h"
 #include "amdlib.h"
 #include <northbridge/amd/agesa/BiosCallOuts.h>
+#include <northbridge/amd/agesa/state_machine.h>
 #include "Ids.h"
 #include "heapManager.h"
 #include "FchPlatform.h"
 #include "cbfs.h"
 #include <stdlib.h>
 
-static AGESA_STATUS Fch_Oem_config(UINT32 Func, UINTN FchData, VOID *ConfigPtr);
-
 const BIOS_CALLOUT_STRUCT BiosCallouts[] =
 {
 	{AGESA_DO_RESET,                 agesa_Reset },
@@ -34,42 +33,14 @@ const BIOS_CALLOUT_STRUCT BiosCallouts[] =
 	{AGESA_GET_IDS_INIT_DATA,        agesa_EmptyIdsInitData },
 	{AGESA_HOOKBEFORE_DQS_TRAINING,  agesa_NoopSuccess },
 	{AGESA_HOOKBEFORE_EXIT_SELF_REF, agesa_NoopSuccess },
-	{AGESA_FCH_OEM_CALLOUT,          Fch_Oem_config },
 	{AGESA_GNB_GFX_GET_VBIOS_IMAGE,  agesa_GfxGetVbiosImage }
 };
 const int BiosCalloutsLen = ARRAY_SIZE(BiosCallouts);
 
-/**
- * Fch Oem setting callback
- *
- *  Configure platform specific Hudson device,
- *   such Azalia, SATA, IMC etc.
- */
-static AGESA_STATUS Fch_Oem_config(UINT32 Func, UINTN FchData, VOID *ConfigPtr)
+void board_FCH_InitReset(struct sysinfo *cb_NA, FCH_RESET_DATA_BLOCK *FchParams_reset)
 {
-	AMD_CONFIG_PARAMS *StdHeader = ConfigPtr;
-
-	if (StdHeader->Func == AMD_INIT_RESET) {
-		FCH_RESET_DATA_BLOCK *FchParams_reset = (FCH_RESET_DATA_BLOCK *)FchData;
-		printk(BIOS_DEBUG, "Fch OEM config in INIT RESET ");
-		//FchParams_reset->EcChannel0 = TRUE; /* logical devicd 3 */
-		FchParams_reset->FchReset.Xhci0Enable = IS_ENABLED(CONFIG_HUDSON_XHCI_ENABLE);
-		FchParams_reset->FchReset.Xhci1Enable = FALSE;
-	} else if (StdHeader->Func == AMD_INIT_ENV) {
-		FCH_DATA_BLOCK *FchParams_env = (FCH_DATA_BLOCK *)FchData;
-		printk(BIOS_DEBUG, "Fch OEM config in INIT ENV ");
-
-		/* Azalia Controller Front Panel OEM Table Pointer */
-
-		/* Fan Control */
-
-		/* XHCI configuration */
-		FchParams_env->Usb.Xhci0Enable = IS_ENABLED(CONFIG_HUDSON_XHCI_ENABLE);
-		FchParams_env->Usb.Xhci1Enable = FALSE;
-
-		/* sata configuration */
-	}
-	printk(BIOS_DEBUG, "Done\n");
+}
 
-	return AGESA_SUCCESS;
+void board_FCH_InitEnv(struct sysinfo *cb_NA, FCH_DATA_BLOCK *FchParams_env)
+{
 }
diff --git a/src/mainboard/hp/abm/Kconfig b/src/mainboard/hp/abm/Kconfig
index 324863202f..fa6bf3cdc7 100644
--- a/src/mainboard/hp/abm/Kconfig
+++ b/src/mainboard/hp/abm/Kconfig
@@ -18,7 +18,6 @@ if BOARD_HP_ABM
 
 config BOARD_SPECIFIC_OPTIONS # dummy
 	def_bool y
-	select AGESA_LEGACY
 	select CPU_AMD_AGESA_FAMILY16_KB
 	select NORTHBRIDGE_AMD_AGESA_FAMILY16_KB
 	select SOUTHBRIDGE_AMD_AGESA_YANGTZE
diff --git a/src/mainboard/hp/abm/OemCustomize.c b/src/mainboard/hp/abm/OemCustomize.c
index 730c97e26e..4eab307c98 100644
--- a/src/mainboard/hp/abm/OemCustomize.c
+++ b/src/mainboard/hp/abm/OemCustomize.c
@@ -21,7 +21,7 @@
 #include <PlatformMemoryConfiguration.h>
 #include "Filecode.h"
 
-#include <northbridge/amd/agesa/agesawrapper.h>
+#include <northbridge/amd/agesa/state_machine.h>
 
 #define FILECODE PROC_GNB_PCIE_FAMILY_0X15_F15PCIECOMPLEXCONFIG_FILECODE
 
@@ -99,6 +99,13 @@ static const PCIe_COMPLEX_DESCRIPTOR PcieComplex = {
 	.DdiLinkList  = DdiList
 };
 
+void board_BeforeInitReset(struct sysinfo *cb, AMD_RESET_PARAMS *Reset)
+{
+	FCH_RESET_INTERFACE *FchReset = &Reset->FchInterface;
+	FchReset->Xhci0Enable = IS_ENABLED(CONFIG_HUDSON_XHCI_ENABLE);
+	FchReset->Xhci1Enable = FALSE;
+}
+
 /*---------------------------------------------------------------------------------------*/
 /**
  *  OemCustomizeInitEarly
@@ -116,7 +123,7 @@ static const PCIe_COMPLEX_DESCRIPTOR PcieComplex = {
  **/
 /*---------------------------------------------------------------------------------------*/
 
-static AGESA_STATUS OemInitEarly(AMD_EARLY_PARAMS * InitEarly)
+void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly)
 {
 	AGESA_STATUS            Status;
 	PCIe_COMPLEX_DESCRIPTOR *PcieComplexListPtr;
@@ -138,14 +145,6 @@ static AGESA_STATUS OemInitEarly(AMD_EARLY_PARAMS * InitEarly)
 	PcieComplexListPtr  =  (PCIe_COMPLEX_DESCRIPTOR *) AllocHeapParams.BufferPtr;
 	LibAmdMemCopy  (PcieComplexListPtr, &PcieComplex, sizeof(PcieComplex), &InitEarly->StdHeader);
 	InitEarly->GnbConfig.PcieComplexList = PcieComplexListPtr;
-	return AGESA_SUCCESS;
-}
-
-static AGESA_STATUS OemInitMid(AMD_MID_PARAMS * InitMid)
-{
-	/* 0 iGpuVgaAdapter, 1 iGpuVgaNonAdapter; */
-	InitMid->GnbMidConfiguration.iGpuVgaMode = 0;
-	return AGESA_SUCCESS;
 }
 
 /*----------------------------------------------------------------------------------------
@@ -159,7 +158,7 @@ static AGESA_STATUS OemInitMid(AMD_MID_PARAMS * InitMid)
  *  is populated, AGESA will base its settings on the data from the table. Otherwise, it will
  *  use its default conservative settings.
  */
-CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = {
+static CONST PSO_ENTRY ROMDATA PlatformMemoryTable[] = {
 	#define SEED_A 0x12
 	HW_RXEN_SEED(
 		ANY_SOCKET, CHANNEL_A, ALL_DIMMS,
@@ -178,7 +177,13 @@ CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = {
   PSO_END
 };
 
-const struct OEM_HOOK OemCustomize = {
-	.InitEarly = OemInitEarly,
-	.InitMid = OemInitMid,
-};
+void board_BeforeInitPost(struct sysinfo *cb, AMD_POST_PARAMS *InitPost)
+{
+	InitPost->MemConfig.PlatformMemoryConfiguration = (PSO_ENTRY *)PlatformMemoryTable;
+}
+
+void board_BeforeInitMid(struct sysinfo *cb, AMD_MID_PARAMS *InitMid)
+{
+	/* 0 iGpuVgaAdapter, 1 iGpuVgaNonAdapter; */
+	InitMid->GnbMidConfiguration.iGpuVgaMode = 0;
+}
diff --git a/src/mainboard/hp/abm/mainboard.c b/src/mainboard/hp/abm/mainboard.c
index 863d7a5b89..4af8678843 100644
--- a/src/mainboard/hp/abm/mainboard.c
+++ b/src/mainboard/hp/abm/mainboard.c
@@ -20,7 +20,7 @@
 #include <arch/io.h>
 #include <arch/acpi.h>
 #include <northbridge/amd/agesa/BiosCallOuts.h>
-#include <northbridge/amd/agesa/agesawrapper.h>
+#include <northbridge/amd/agesa/state_machine.h>
 #include <southbridge/amd/common/amd_pci_util.h>
 #include <southbridge/amd/agesa/hudson/pci_devs.h>
 #include <northbridge/amd/agesa/family16kb/pci_devs.h>
@@ -113,9 +113,6 @@ static void mainboard_enable(device_t dev)
 {
 	printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n");
 
-	if (acpi_is_wakeup_s3())
-		agesawrapper_fchs3earlyrestore();
-
 	/* Initialize the PIRQ data structures for consumption */
 	pirq_setup();
 }
diff --git a/src/mainboard/hp/abm/romstage.c b/src/mainboard/hp/abm/romstage.c
index 79a8fa5692..88ba01a29c 100644
--- a/src/mainboard/hp/abm/romstage.c
+++ b/src/mainboard/hp/abm/romstage.c
@@ -14,46 +14,35 @@
  * GNU General Public License for more details.
  */
 
-#include <stdint.h>
-#include <string.h>
-#include <device/pci_def.h>
-#include <device/pci_ids.h>
-#include <arch/acpi.h>
 #include <arch/io.h>
-#include <arch/stages.h>
 #include <device/pnp_def.h>
-#include <arch/cpu.h>
-#include <cpu/x86/lapic.h>
-#include <console/console.h>
-#include <commonlib/loglevel.h>
-#include <cpu/amd/car.h>
-#include <northbridge/amd/agesa/agesawrapper.h>
-#include <northbridge/amd/agesa/agesa_helper.h>
-#include <cpu/x86/bist.h>
-#include <cpu/x86/lapic.h>
+#include <northbridge/amd/agesa/state_machine.h>
 #include <southbridge/amd/agesa/hudson/hudson.h>
-#include <cpu/amd/agesa/s3_resume.h>
-#include <cbmem.h>
 #include <superio/nuvoton/common/nuvoton.h>
 #include <superio/nuvoton/nct5104d/nct5104d.h>
 
 #define SERIAL_DEV PNP_DEV(0x4E, NCT5104D_SP4)
 
-void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
+void board_BeforeAgesa(struct sysinfo *cb)
 {
-	u32 val, t32;
 	u32 *addr32;
+	u32 t32;
 
-
-	/* Must come first to enable PCI MMCONF. */
-	amd_initmmio();
-
-	/* Set LPC decode enables. */
+	/* For serial port option, plug-in card on LPC. */
 	pci_devfn_t dev = PCI_DEV(0, 0x14, 3);
 	pci_write_config32(dev, 0x44, 0xff03ffd5);
 
 	hudson_lpc_port80();
 
+	/* In Hudson RRG, PMIOxD2[5:4] is "Drive strength control for
+	 *  LpcClk[1:0]".  To be consistent with Parmer, setting to 4mA
+	 *  even though the register is not documented in the Kabini BKDG.
+	 *  Otherwise the serial output is bad code.
+	 */
+	outb(0xD2, 0xcd6);
+	outb(0x00, 0xcd7);
+
+
 	/* Enable the AcpiMmio space */
 	outb(0x24, 0xcd6);
 	outb(0x01, 0xcd7);
@@ -72,58 +61,12 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	t32 &= 0xffffff7b; // clear 2, 7
 	*addr32 = t32;
 
-	if (!cpu_init_detectedx && boot_cpu()) {
-		post_code(0x30);
-		post_code(0x31);
-
-		nct5104d_enable_uartd(SERIAL_DEV);
-		nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
-		console_init();
-	}
-
-	/* Halt if there was a built in self test failure */
-	post_code(0x34);
-	report_bist_failure(bist);
-
-	/* Load MPB */
-	val = cpuid_eax(1);
-	printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val);
-	printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx);
-
-	post_code(0x37);
-	agesawrapper_amdinitreset();
-	post_code(0x38);
-	printk(BIOS_DEBUG, "Got past yangtze_early_setup\n");
-
-	post_code(0x39);
-
-	agesawrapper_amdinitearly();
-	int s3resume = acpi_is_wakeup_s3();
-	if (!s3resume) {
-		post_code(0x40);
-		agesawrapper_amdinitpost();
-		post_code(0x41);
-		agesawrapper_amdinitenv();
-		/* TODO: Disable cache is not ok. */
-		disable_cache_as_ram();
-	} else { /* S3 detect */
-		printk(BIOS_INFO, "S3 detected\n");
-
-		post_code(0x60);
-		agesawrapper_amdinitresume();
-
-		amd_initcpuio();
-		agesawrapper_amds3laterestore();
-
-		post_code(0x61);
-		prepare_for_resume();
-	}
+	nct5104d_enable_uartd(SERIAL_DEV);
+	nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
+}
 
+#if 0
+	/* Was before copy_and_run. */
 	outb(0xEA, 0xCD6);
 	outb(0x1, 0xcd7);
-
-	post_code(0x50);
-	copy_and_run();
-
-	post_code(0x54);  /* Should never see this post code. */
-}
+#endif