mb/intel/tglrvp: add Tiger Lake memory initialization support

Update memory parameters based on memory type supported by Tiger lake RVP
1. Update dq/dqs mappings
2. Update spd data for Tiger lake LPDDR4 SAMSUNG/MICRON memory
3. Add SPD data bin files for supported memory types
4. Update other FSPM UPDs as part of memory initialization

BUG=none
BRANCH=none
TEST= build tglrvp flash and boot to kernel

Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Change-Id: I7248862efd1dcd5a0df0e17d39b44c168caa200e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38998
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>

10 files changed, 245 insertions, 19 deletions

diff --git a/src/mainboard/intel/tglrvp/board_id.h b/src/mainboard/intel/tglrvp/board_id.h
index 9aac527ad0..364f4f7b04 100644
--- a/src/mainboard/intel/tglrvp/board_id.h
+++ b/src/mainboard/intel/tglrvp/board_id.h
@@ -1,7 +1,7 @@
 /*
  * This file is part of the coreboot project.
  *
- * Copyright (C) 2019 Intel Corporation.
+ * Copyright (C) 2019-2020 Intel Corporation.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -21,6 +21,11 @@
 /* Board/FAB ID Command */
 #define EC_FAB_ID_CMD	0x0D
 
+/* TGL-U Board IDs */
+#define TGL_U_LP4_SAMSUNG	0x3
+#define TGL_U_LP4_HYNIX		0xB
+#define TGL_U_LP4_MICRON	0x13
+
 /*
  * Returns board information (board id[15:8] and
  * Fab info[7:0]) on success and < 0 on error
diff --git a/src/mainboard/intel/tglrvp/romstage_fsp_params.c b/src/mainboard/intel/tglrvp/romstage_fsp_params.c
index 0ab1f48fee..89ae0ab3fb 100644
--- a/src/mainboard/intel/tglrvp/romstage_fsp_params.c
+++ b/src/mainboard/intel/tglrvp/romstage_fsp_params.c
@@ -1,7 +1,7 @@
 /*
  * This file is part of the coreboot project.
  *
- * Copyright (C) 2019 Intel Corporation.
+ * Copyright (C) 2019-2020 Intel Corporation.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -12,11 +12,55 @@
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
  */
-
+#include <assert.h>
+#include <console/console.h>
 #include <fsp/api.h>
 #include <soc/romstage.h>
+#include <spd_bin.h>
+#include <string.h>
+#include <soc/meminit_tgl.h>
+#include <baseboard/variants.h>
+#include <cbfs.h>
+#include "board_id.h"
+#include "spd/spd.h"
+
+static uintptr_t mainboard_get_spd_index(void)
+{
+	uint8_t board_id = (get_board_id() & 0xFF);
+	int spd_index;
+
+	printk(BIOS_INFO, "board id is 0x%x\n", board_id);
+
+	switch (board_id) {
+	case TGL_U_LP4_MICRON:
+		spd_index = SPD_ID_MICRON;
+		break;
+	case TGL_U_LP4_SAMSUNG:
+		spd_index = SPD_ID_SAMSUNG;
+		break;
+	case TGL_U_LP4_HYNIX:
+		spd_index = SPD_ID_HYNIX;
+		break;
+	default:
+		spd_index = SPD_ID_MICRON;
+		printk(BIOS_WARNING, "Invalid board_id 0x%x\n", board_id);
+	}
+
+	printk(BIOS_INFO, "SPD index is 0x%x\n", spd_index);
+	return spd_index;
+}
 
 void mainboard_memory_init_params(FSPM_UPD *mupd)
 {
-	/* ToDo : Fill FSP-M memory params */
+	FSP_M_CONFIG *mem_cfg = &mupd->FspmConfig;
+
+	const struct mb_lpddr4x_cfg *mem_config = variant_memory_params();
+	const struct spd_info spd_info = {
+		.read_type = READ_SPD_CBFS,
+		.spd_spec.spd_index = mainboard_get_spd_index(),
+	};
+	bool half_populated = false;
+
+	meminit_lpddr4x_dimm0(mem_cfg, mem_config, &spd_info, half_populated);
+
 }
diff --git a/src/mainboard/intel/tglrvp/spd/Hynix-H9HKNNNEBMAV-4267.spd.hex b/src/mainboard/intel/tglrvp/spd/Hynix-H9HKNNNEBMAV-4267.spd.hex
new file mode 100644
index 0000000000..2ff9ed382e
--- /dev/null
+++ b/src/mainboard/intel/tglrvp/spd/Hynix-H9HKNNNEBMAV-4267.spd.hex
@@ -0,0 +1,32 @@
+23 11 11 0E 1B 21 F9 08 00 40 00 00 0A 01 00 00
+00 00 05 0F 92 54 01 00 8A 00 90 A8 90 C0 08 60
+04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 92 00 A7 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 56 00 00 00 20 20 20 20 20 20 20
+20 20 20 20 20 20 20 20 20 20 20 20 20 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
diff --git a/src/mainboard/intel/tglrvp/spd/Makefile.inc b/src/mainboard/intel/tglrvp/spd/Makefile.inc
index b8b059a1b7..21ea65e807 100644
--- a/src/mainboard/intel/tglrvp/spd/Makefile.inc
+++ b/src/mainboard/intel/tglrvp/spd/Makefile.inc
@@ -1,7 +1,7 @@
 ##
 ## This file is part of the coreboot project.
 ##
-## Copyright (C) 2019 Intel Corporation.
+## Copyright (C) 2019-2020 Intel Corporation.
 ##
 ## This program is free software; you can redistribute it and/or modify
 ## it under the terms of the GNU General Public License as published by
@@ -13,8 +13,22 @@
 ## GNU General Public License for more details.
 ##
 
-romstage-y += spd_util.c
-
 SPD_BIN = $(obj)/spd.bin
 
-SPD_SOURCES = empty	# 0b000
+SPD_SOURCES = Micron-MT53D1G64D8SQ-046
+SPD_SOURCES += Samsung-K4UBE3D4AA-MGCL
+SPD_SOURCES += Hynix-H9HKNNNEBMAV-4267
+
+SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex)
+
+# Include spd ROM data
+$(SPD_BIN): $(SPD_DEPS)
+	for f in $+; \
+	  do for c in $$(cat $$f | grep -v ^#); \
+	    do printf $$(printf '\%o' 0x$$c); \
+	  done; \
+	done > $@
+
+cbfs-files-y += spd.bin
+spd.bin-file := $(SPD_BIN)
+spd.bin-type := spd
diff --git a/src/mainboard/intel/tglrvp/spd/Micron-MT53D1G64D8SQ-046.spd.hex b/src/mainboard/intel/tglrvp/spd/Micron-MT53D1G64D8SQ-046.spd.hex
new file mode 100644
index 0000000000..40fccaa76d
--- /dev/null
+++ b/src/mainboard/intel/tglrvp/spd/Micron-MT53D1G64D8SQ-046.spd.hex
@@ -0,0 +1,32 @@
+23 10 11 0E 15 19 95 08 00 40 00 00 02 21 00 00
+48 00 05 FF 92 55 00 00 8C 00 90 A8 90 90 06 D0
+02 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 7F 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 55 00 00 00 20 20 20 20 20 20 20
+20 20 20 20 20 20 20 20 20 20 20 20 20 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
diff --git a/src/mainboard/intel/tglrvp/spd/Samsung-K4UBE3D4AA-MGCL.spd.hex b/src/mainboard/intel/tglrvp/spd/Samsung-K4UBE3D4AA-MGCL.spd.hex
new file mode 100644
index 0000000000..945b2e8e06
--- /dev/null
+++ b/src/mainboard/intel/tglrvp/spd/Samsung-K4UBE3D4AA-MGCL.spd.hex
@@ -0,0 +1,32 @@
+23 11 11 0E 15 21 B5 08 00 40 00 00 0A 21 00 00
+48 00 04 0F 92 54 05 00 87 00 90 A8 90 C0 08 60
+04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 E0 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 20 00 00 00 20 20 20 20 20 20 20
+20 20 20 20 20 20 20 20 20 20 20 20 20 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
diff --git a/src/mainboard/intel/tglrvp/spd/spd.h b/src/mainboard/intel/tglrvp/spd/spd.h
index ed8b8b6e0d..9e746243cc 100644
--- a/src/mainboard/intel/tglrvp/spd/spd.h
+++ b/src/mainboard/intel/tglrvp/spd/spd.h
@@ -1,7 +1,7 @@
 /*
  * This file is part of the coreboot project.
  *
- * Copyright (C) 2019 Intel Corporation.
+ * Copyright (C) 2019-2020 Intel Corporation.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -16,14 +16,16 @@
 #ifndef MAINBOARD_SPD_H
 #define MAINBOARD_SPD_H
 
-#include <stdint.h>
+/* SPD index definition should be matched with the order of SPD_SOURCES */
+#define SPD_ID_MICRON		0x0
+#define SPD_ID_SAMSUNG		0x1
+#define SPD_ID_HYNIX		0x2
 
-#define RCOMP_TARGET_PARAMS	0x5
+void mainboard_fill_dq_map_ch0(void *dq_map_ptr);
+void mainboard_fill_dq_map_ch1(void *dq_map_ptr);
+void mainboard_fill_dqs_map_ch0(void *dqs_map_ptr);
+void mainboard_fill_dqs_map_ch1(void *dqs_map_ptr);
+void mainboard_fill_rcomp_res_data(void *rcomp_ptr);
+void mainboard_fill_rcomp_strength_data(void *rcomp_strength_ptr);
 
-void mainboard_fill_dq_map_ch0(u8 *dq_map_ptr);
-void mainboard_fill_dq_map_ch1(u8 *dq_map_ptr);
-void mainboard_fill_dqs_map_ch0(u8 *dqs_map_ptr);
-void mainboard_fill_dqs_map_ch1(u8 *dqs_map_ptr);
-void mainboard_fill_rcomp_res_data(u16 *rcomp_ptr);
-void mainboard_fill_rcomp_strength_data(u16 *rcomp_strength_ptr);
 #endif
diff --git a/src/mainboard/intel/tglrvp/variants/baseboard/include/baseboard/variants.h b/src/mainboard/intel/tglrvp/variants/baseboard/include/baseboard/variants.h
index 9220b1140c..25c9755d9d 100644
--- a/src/mainboard/intel/tglrvp/variants/baseboard/include/baseboard/variants.h
+++ b/src/mainboard/intel/tglrvp/variants/baseboard/include/baseboard/variants.h
@@ -1,7 +1,7 @@
 /*
  * This file is part of the coreboot project.
  *
- * Copyright (C) 2019 Intel Corporation.
+ * Copyright (C) 2019-2020 Intel Corporation.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -17,6 +17,7 @@
 #define __BASEBOARD_VARIANTS_H__
 
 #include <soc/gpio.h>
+#include <soc/meminit_tgl.h>
 #include <stdint.h>
 #include <vendorcode/google/chromeos/chromeos.h>
 
@@ -27,4 +28,7 @@ const struct pad_config *variant_gpio_table(size_t *num);
 const struct pad_config *variant_early_gpio_table(size_t *num);
 const struct cros_gpio *variant_cros_gpios(size_t *num);
 
+size_t variant_memory_sku(void);
+const struct mb_lpddr4x_cfg *variant_memory_params(void);
+
 #endif /*__BASEBOARD_VARIANTS_H__ */
diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/Makefile.inc b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/Makefile.inc
index 23bf160883..c272607042 100644
--- a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/Makefile.inc
+++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/Makefile.inc
@@ -1,7 +1,7 @@
 ##
 ## This file is part of the coreboot project.
 ##
-## Copyright (C) 2019 Intel Corporation.
+## Copyright (C) 2019-2020 Intel Corporation.
 ##
 ## This program is free software; you can redistribute it and/or modify
 ## it under the terms of the GNU General Public License as published by
@@ -15,4 +15,6 @@
 
 bootblock-y += gpio.c
 
+romstage-y += memory.c
+
 ramstage-y += gpio.c
diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/memory.c b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/memory.c
new file mode 100644
index 0000000000..67979b649b
--- /dev/null
+++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/memory.c
@@ -0,0 +1,59 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2020 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <arch/cpu.h>
+#include <baseboard/variants.h>
+#include <intelblocks/mp_init.h>
+
+size_t __weak variant_memory_sku(void)
+{
+	return 0;
+}
+
+static const struct mb_lpddr4x_cfg mem_config = {
+	/* DQ byte map */
+	.dq_map = {
+	{  0,  1,  6,  7,  3,  2,  5,  4,    /* Byte 0 */
+	  15,  8,  9, 14, 12, 11, 10, 13 },  /* Byte 1 */
+	{ 11, 12,  8, 15,  9, 14, 10, 13,    /* Byte 2 */
+	   3,  4,  7,  0,  6,  1,  5,  2 },  /* Byte 3 */
+	{  4,  5,  3,  2,  7,  1,  0,  6,    /*	Byte 4 */
+	  11, 10, 12, 13,  8,  9, 14, 15 },  /* Byte 5 */
+	{ 12, 11,  8, 13, 14, 15,  9, 10,    /* Byte 6 */
+	   4,  7,  3,  2,  1,  6,  0,  5 },  /* Byte 7 */
+	{ 11, 10,  9,  8, 12, 13, 15, 14,    /* Byte 0 */
+	   4,  5,  6,  7,  3,  2,  0,  1 },  /* Byte 1 */
+	{  0,  7,  1,  6,  3,  5,  2,  4,    /* Byte 2 */
+	   9,  8, 10, 11, 14, 15, 13, 12 },  /* Byte 3 */
+	{  4,  5,  6,  1,  3,  2,  7,  0,    /* Byte 4 */
+	  10, 13, 12, 11, 14,  9, 15,  8 },  /* Byte 5 */
+	{ 10, 12,  9, 15,  8, 11, 13, 14,    /* Byte 6 */
+	   3,  4,  1,  2,  6,  0,  5,  7 }   /* Byte 7 */
+	},
+
+	/* DQS CPU<>DRAM map */
+	.dqs_map = {
+	/* Ch 0     1         2         3  */
+	{ 0, 1 }, { 1, 0 }, { 0, 1 }, { 1, 0 },
+	{ 1, 0 }, { 0, 1 }, { 0, 1 }, { 1, 0 }
+	},
+
+	.ect = 1, /* Early Command Training */
+};
+
+const struct mb_lpddr4x_cfg *__weak variant_memory_params(void)
+{
+	return &mem_config;
+}