diff options
| author | Mario Scheithauer <mario.scheithauer@siemens.com> | 2017-07-18 15:19:18 +0200 |
|---|---|---|
| committer | Werner Zeh <werner.zeh@siemens.com> | 2017-07-20 04:44:58 +0000 |
| commit | 05a2b1aacdc9f8c47d6e0f857a0429b54816ca48 (patch) | |
| tree | 8aa4a32125dadf045ed020fa86629bf7022d3f19 /src/mainboard | |
| parent | d27a565211a7bbd647599efe69695686de142e51 (diff) | |
| download | coreboot-05a2b1aacdc9f8c47d6e0f857a0429b54816ca48.tar.xz | |
siemens/mc_apl1: Activate ECC for DRAM
This mainboard is equipped with DDR3L modules which support ECC. The
BWG says that for activating ECC the FSP-M parameter MemoryDown must be
set to 5.
Change-Id: Idc68df1e2bae2396c9b9788d4a026a75b7d9119b
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/20634
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Diffstat (limited to 'src/mainboard')
| -rw-r--r-- | src/mainboard/siemens/mc_apl1/romstage.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/mainboard/siemens/mc_apl1/romstage.c b/src/mainboard/siemens/mc_apl1/romstage.c index 3347f23450..3462c76c13 100644 --- a/src/mainboard/siemens/mc_apl1/romstage.c +++ b/src/mainboard/siemens/mc_apl1/romstage.c @@ -57,7 +57,7 @@ void mainboard_memory_init_params(FSPM_UPD *memupd) /* DRAM Config settings */ memupd->FspmConfig.Package = 0x1; memupd->FspmConfig.Profile = 0x19; - memupd->FspmConfig.MemoryDown = 0x1; + memupd->FspmConfig.MemoryDown = 0x5; memupd->FspmConfig.DDR3LPageSize = 0x2; memupd->FspmConfig.DDR3LASR = 0x0; memupd->FspmConfig.ScramblerSupport = 0x0; |