diff options
author | Stefan Reinauer <reinauer@chromium.org> | 2014-01-07 09:53:06 -0800 |
---|---|---|
committer | Patrick Georgi <patrick@georgi-clan.de> | 2014-07-12 20:16:53 +0200 |
commit | 1abeef60054f8e3d5b618a88c411d98591a5f4a3 (patch) | |
tree | 8b3ad71fd91ebe228a5637942a322c4082b53cf0 /src/mainboard | |
parent | 84570d6c5b8536ca9e7d267fbdcda6375661882a (diff) | |
download | coreboot-1abeef60054f8e3d5b618a88c411d98591a5f4a3.tar.xz |
google/panther: Add ACPI code to support wake-on-lan
There needs to be an ACPI linkage to provide the power resource
needed to wake this device so the kernel will enable the SCI
before going to suspend.
A link is added for both NIC and WLAN, but it is only tested
on the NIC.
This is a forward port from Duncan's beltino patch.
BUG=chrome-os-partner:24657
BRANCH=panther
TEST=build and boot on panther, suspend and wake with etherwake
Change-Id: I2804d2e904e26d6e34f5a177f0dabc1aaa3f0288
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Reviewed-by: Stefan Reinauer <reinauer@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/181752
Commit-Queue: Stefan Reinauer <reinauer@chromium.org>
Tested-by: Stefan Reinauer <reinauer@chromium.org>
Reviewed-on: http://review.coreboot.org/5998
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Diffstat (limited to 'src/mainboard')
-rw-r--r-- | src/mainboard/google/panther/acpi/mainboard.asl | 45 | ||||
-rw-r--r-- | src/mainboard/google/panther/dsdt.asl | 4 | ||||
-rw-r--r-- | src/mainboard/google/panther/onboard.h | 12 |
3 files changed, 60 insertions, 1 deletions
diff --git a/src/mainboard/google/panther/acpi/mainboard.asl b/src/mainboard/google/panther/acpi/mainboard.asl index 59ed710dad..867c1e03ea 100644 --- a/src/mainboard/google/panther/acpi/mainboard.asl +++ b/src/mainboard/google/panther/acpi/mainboard.asl @@ -19,11 +19,56 @@ * MA 02110-1301 USA */ +#include <mainboard/google/panther/onboard.h> + Scope (\_SB) { Device (PWRB) { Name(_HID, EisaId("PNP0C0C")) } +} + +/* + * LAN connected to Root Port 3, becomes Root Port 1 after coalesce + */ +Scope (\_SB.PCI0.RP01) +{ + Device (ETH0) + { + Name (_ADR, 0x00000000) + Name (_PRW, Package() { PANTHER_NIC_WAKE_GPIO, 3 }) + + Method (_DSW, 3, NotSerialized) + { + Store (PANTHER_NIC_WAKE_GPIO, Local0) + + If (LEqual (Arg0, 1)) { + // Enable GPIO as wake source + \_SB.PCI0.LPCB.GWAK (Local0) + } + } + } +} +/* + * WLAN connected to Root Port 4, becomes Root Port 2 after coalesce + */ +Scope (\_SB.PCI0.RP02) +{ + Device (WLAN) + { + Name (_ADR, 0x00000000) + Name (_PRW, Package() { PANTHER_WLAN_WAKE_GPIO, 3 }) + + Method (_DSW, 3, NotSerialized) + { + Store (PANTHER_WLAN_WAKE_GPIO, Local0) + + If (LEqual (Arg0, 1)) { + // Enable GPIO as wake source + \_SB.PCI0.LPCB.GWAK (Local0) + } + } + } } diff --git a/src/mainboard/google/panther/dsdt.asl b/src/mainboard/google/panther/dsdt.asl index 1316ebfcd3..87076fee08 100644 --- a/src/mainboard/google/panther/dsdt.asl +++ b/src/mainboard/google/panther/dsdt.asl @@ -31,7 +31,6 @@ DefinitionBlock( { // Some generic macros #include "acpi/platform.asl" - #include "acpi/mainboard.asl" // global NVS and variables #include <southbridge/intel/lynxpoint/acpi/globalnvs.asl> @@ -50,6 +49,9 @@ DefinitionBlock( } } + // Mainboard devices + #include "acpi/mainboard.asl" + // Thermal handler #include "acpi/thermal.asl" diff --git a/src/mainboard/google/panther/onboard.h b/src/mainboard/google/panther/onboard.h index 794dd8d7f8..0b67017113 100644 --- a/src/mainboard/google/panther/onboard.h +++ b/src/mainboard/google/panther/onboard.h @@ -1,4 +1,9 @@ +#ifndef __MAINBOARD_ONBOARD_H +#define __MAINBOARD_ONBOARD_H + +#ifndef __ACPI__ void lan_init(void); +#endif /* defines for programming the MAC address */ #define PANTHER_NIC_VENDOR_ID 0x10EC @@ -7,3 +12,10 @@ void lan_init(void); /* 0x00: White LINK LED and Amber ACTIVE LED */ #define PANTHER_NIC_LED_MODE 0x00 +/* NIC wake is GPIO 8 */ +#define PANTHER_NIC_WAKE_GPIO 8 + +/* WLAN wake is GPIO 10 */ +#define PANTHER_WLAN_WAKE_GPIO 10 + +#endif |