diff options
| author | Brandon Breitenstein <brandon.breitenstein@intel.com> | 2020-07-23 14:40:14 -0700 |
|---|---|---|
| committer | Duncan Laurie <dlaurie@chromium.org> | 2020-08-14 16:03:03 +0000 |
| commit | 228d0e50789674be848f68f35f40570d8c3dd49c (patch) | |
| tree | 45685a63138e4d2ac684353c02703b989fde5b19 /src/mainboard | |
| parent | 041fcf59025bb1801828441e09b2f56b48e12fdc (diff) | |
| download | coreboot-228d0e50789674be848f68f35f40570d8c3dd49c.tar.xz | |
mb/google/volteer: Only enable TBT root ports if USB4 is supported
TBT ports should be disabled if the DB is a USB3 DB. It is assumed if
the DB doesn't support USB4 the platform as a whole should only be USB3
capable and TBT functionality on both ports should not be enabled.
BUG=NONE
BRANCH=NONE
TEST=Built coreboot and verified that TBT was disabled on platform with
USB3 DB and enabled on platform with USB4/TBT DB
Change-Id: I594f2e9483aaf896de2b6aea9a3460bd3826c58c
Signed-off-by: Brandon Breitenstein <brandon.breitenstein@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43771
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'src/mainboard')
| -rw-r--r-- | src/mainboard/google/volteer/variants/baseboard/devicetree.cb | 15 |
1 files changed, 12 insertions, 3 deletions
diff --git a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb index 53bbe5a0c0..57ab9e42c5 100644 --- a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb @@ -381,8 +381,14 @@ chip soc/intel/tigerlake end # DPTF 0x9A03 device pci 05.0 off end # IPU 0x9A19 device pci 06.0 off end # PEG60 0x9A09 - device pci 07.0 on end # TBT_PCIe0 0x9A23 - device pci 07.1 on end # TBT_PCIe1 0x9A25 + device pci 07.0 on # TBT_PCIe0 0x9A23 + probe DB_USB USB4_GEN2 + probe DB_USB USB4_GEN3 + end + device pci 07.1 on # TBT_PCIe1 0x9A25 + probe DB_USB USB4_GEN2 + probe DB_USB USB4_GEN3 + end device pci 07.2 off end # TBT_PCIe2 0x9A27 device pci 07.3 off end # TBT_PCIe3 0x9A29 device pci 08.0 on end # GNA 0x9A11 @@ -390,7 +396,10 @@ chip soc/intel/tigerlake device pci 0a.0 off end # Crash-log SRAM 0x9A0D device pci 0d.0 on end # USB xHCI 0x9A13 device pci 0d.1 off end # USB xDCI (OTG) 0x9A15 - device pci 0d.2 on end # TBT DMA0 0x9A1B + device pci 0d.2 on # TBT DMA0 0x9A1B + probe DB_USB USB4_GEN2 + probe DB_USB USB4_GEN3 + end device pci 0d.3 off end # TBT DMA1 0x9A1D device pci 0e.0 off end # VMD 0x9A0B |