diff options
| author | Bora Guvendik <bora.guvendik@intel.com> | 2019-09-27 22:26:49 -0700 |
|---|---|---|
| committer | Subrata Banik <subrata.banik@intel.com> | 2019-09-30 04:51:31 +0000 |
| commit | 6aeed16422df88c697d034ed4688ab44e41fa070 (patch) | |
| tree | afba1d4a69204eb6272c8b66e6b00449c3f89d6c /src/mainboard | |
| parent | b09d44ef2d6faf9c0f7762b8385b894224d5929a (diff) | |
| download | coreboot-6aeed16422df88c697d034ed4688ab44e41fa070.tar.xz | |
mb/google/drallion: Adjust GPD3 pin termination
Internal pull up need to be enabled for GPD3 as power button pin for
PCH according cometlake pch EDS vol1 section 17-1. Without that pin will
stay floating and hook up XDP can cause system shutdown as power buttone
event will trigger.
BUG=N/A
TEST=Hook up XDP on drallion platform, able to boot up into OS and stay
at power up state.
Change-Id: Idd1befeb14a251b7c0542ca1f99049d07b28fb98
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35666
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Diffstat (limited to 'src/mainboard')
| -rw-r--r-- | src/mainboard/google/drallion/variants/drallion/gpio.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/mainboard/google/drallion/variants/drallion/gpio.c b/src/mainboard/google/drallion/variants/drallion/gpio.c index c7b005370c..154fc5a7f2 100644 --- a/src/mainboard/google/drallion/variants/drallion/gpio.c +++ b/src/mainboard/google/drallion/variants/drallion/gpio.c @@ -214,7 +214,6 @@ static const struct pad_config gpio_table[] = { /* BATLOW# */ PAD_CFG_NF(GPD0, NONE, DEEP, NF1), /* BATLOW# */ /* ACPRESENT */ PAD_CFG_NF(GPD1, NONE, DEEP, NF1), /* AC_PRESENT */ /* LAN_WAKE# */ PAD_CFG_NF(GPD2, NONE, DEEP, NF1), /* LAN_WAKE# */ -/* PWRBTN# */ PAD_CFG_NF(GPD3, NONE, DEEP, NF1), /* SIO_PWRBTN# */ /* SLP_S3# */ PAD_CFG_NF(GPD4, NONE, DEEP, NF1), /* SIO_SLP_S3# */ /* SLP_S4# */ PAD_CFG_NF(GPD5, NONE, DEEP, NF1), /* SIO_SLP_S4# */ /* SLP_A# */ PAD_CFG_NF(GPD6, NONE, DEEP, NF1), /* SIO_SLP_A# */ @@ -250,6 +249,7 @@ static const struct pad_config early_gpio_table[] = { /* EMMC_DATA3 */ PAD_CFG_GPI(GPP_F15, NONE, DEEP), /* MEM_CONFIGO_1P8 */ /* EMMC_DATA4 */ PAD_CFG_GPI(GPP_F16, NONE, DEEP), /* MEM_CONFIGO_1P8 */ /* I2C2_SCL */ PAD_CFG_GPI(GPP_H5, NONE, PLTRST), /* 360_SENSOR_DET# */ +/* PWRBTN# */ PAD_CFG_NF(GPD3, UP_20K, DEEP, NF1), /* SIO_PWRBTN# */ }; const struct pad_config *variant_gpio_table(size_t *num) |