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authorUwe Hermann <uwe@hermann-uwe.de>2010-10-06 19:32:39 +0000
committerUwe Hermann <uwe@hermann-uwe.de>2010-10-06 19:32:39 +0000
commit6f2d20ec490a276a087acad0b3866c0f3ee844c4 (patch)
tree8b96891ff7986129f1cee5c556719fd1edc1aa73 /src/mainboard
parent5225520172a1d1e5c19a93c9178ecd7b72a13248 (diff)
downloadcoreboot-6f2d20ec490a276a087acad0b3866c0f3ee844c4.tar.xz
Convert all Intel 440BX boards to Cache-as-RAM (CAR).
- Add "select CACHE_AS_RAM" in src/cpu/intel/slot_1/Kconfig. - Add the following in src/cpu/intel/slot_1/Makefile.inc: cpu_incs += $(src)/cpu/intel/car/cache_as_ram.inc - Remove "select ROMCC" from all 440BX board Kconfig files. - Drop all early_mtrr_init() calls, that's done by CAR code now. Various small fixes were needed to make it build: - Drop do_smbus_recv_byte(), do_smbus_send_byte(), do_smbus_write_byte(), those were never called anyways. - Remove the "static" from the main() functions in romstage.c files. - Always call dump_spd_registers() from the 440BX debug.c, but use "#if CONFIG_DEBUG_RAM_SETUP" to only have that code if RAM debugging is enabled in menuconfig. - Drop all "lib/ramtest.c" #includes and ram_check() calls (even if commented out) from romstage.c's, as we've done for most other boards. - Add missing #includes or prototypes. Some of the prototypes will be removed later when we get rid of the #include'd .c files. Abuild-tested for all boards, and boot-tested on A-Trend ATC-6220. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Patrick Georgi <patrick@georgi-clan.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5917 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard')
-rw-r--r--src/mainboard/a-trend/atc-6220/Kconfig1
-rw-r--r--src/mainboard/a-trend/atc-6220/romstage.c12
-rw-r--r--src/mainboard/a-trend/atc-6240/Kconfig1
-rw-r--r--src/mainboard/a-trend/atc-6240/romstage.c12
-rw-r--r--src/mainboard/abit/be6-ii_v2_0/Kconfig1
-rw-r--r--src/mainboard/abit/be6-ii_v2_0/romstage.c12
-rw-r--r--src/mainboard/asus/p2b-d/Kconfig1
-rw-r--r--src/mainboard/asus/p2b-d/romstage.c14
-rw-r--r--src/mainboard/asus/p2b-ds/Kconfig1
-rw-r--r--src/mainboard/asus/p2b-ds/romstage.c14
-rw-r--r--src/mainboard/asus/p2b-f/Kconfig1
-rw-r--r--src/mainboard/asus/p2b-f/romstage.c12
-rw-r--r--src/mainboard/asus/p2b-ls/Kconfig1
-rw-r--r--src/mainboard/asus/p2b-ls/romstage.c12
-rw-r--r--src/mainboard/asus/p2b/Kconfig1
-rw-r--r--src/mainboard/asus/p2b/romstage.c12
-rw-r--r--src/mainboard/asus/p3b-f/Kconfig1
-rw-r--r--src/mainboard/asus/p3b-f/romstage.c12
-rw-r--r--src/mainboard/azza/pt-6ibd/Kconfig1
-rw-r--r--src/mainboard/azza/pt-6ibd/romstage.c12
-rw-r--r--src/mainboard/biostar/m6tba/Kconfig1
-rw-r--r--src/mainboard/biostar/m6tba/romstage.c12
-rw-r--r--src/mainboard/compaq/deskpro_en_sff_p600/Kconfig1
-rw-r--r--src/mainboard/compaq/deskpro_en_sff_p600/romstage.c12
-rw-r--r--src/mainboard/gigabyte/ga-6bxc/Kconfig1
-rw-r--r--src/mainboard/gigabyte/ga-6bxc/romstage.c13
-rw-r--r--src/mainboard/gigabyte/ga-6bxe/Kconfig1
-rw-r--r--src/mainboard/gigabyte/ga-6bxe/romstage.c12
-rw-r--r--src/mainboard/msi/ms6119/Kconfig1
-rw-r--r--src/mainboard/msi/ms6119/romstage.c12
-rw-r--r--src/mainboard/msi/ms6147/Kconfig1
-rw-r--r--src/mainboard/msi/ms6147/romstage.c21
-rw-r--r--src/mainboard/msi/ms6156/Kconfig1
-rw-r--r--src/mainboard/msi/ms6156/romstage.c12
-rw-r--r--src/mainboard/nokia/ip530/romstage.c11
-rw-r--r--src/mainboard/soyo/sy-6ba-plus-iii/Kconfig1
-rw-r--r--src/mainboard/soyo/sy-6ba-plus-iii/romstage.c13
-rw-r--r--src/mainboard/tyan/s1846/Kconfig1
-rw-r--r--src/mainboard/tyan/s1846/romstage.c12
39 files changed, 66 insertions, 207 deletions
diff --git a/src/mainboard/a-trend/atc-6220/Kconfig b/src/mainboard/a-trend/atc-6220/Kconfig
index fd25410580..3fba3cf1d0 100644
--- a/src/mainboard/a-trend/atc-6220/Kconfig
+++ b/src/mainboard/a-trend/atc-6220/Kconfig
@@ -25,7 +25,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select NORTHBRIDGE_INTEL_I440BX
select SOUTHBRIDGE_INTEL_I82371EB
select SUPERIO_WINBOND_W83977TF
- select ROMCC
select HAVE_PIRQ_TABLE
select UDELAY_TSC
select BOARD_ROMSIZE_KB_256
diff --git a/src/mainboard/a-trend/atc-6220/romstage.c b/src/mainboard/a-trend/atc-6220/romstage.c
index a0a1cee39f..a55997fae9 100644
--- a/src/mainboard/a-trend/atc-6220/romstage.c
+++ b/src/mainboard/a-trend/atc-6220/romstage.c
@@ -26,16 +26,15 @@
#include <arch/hlt.h>
#include <stdlib.h>
#include <console/console.h>
-#include "lib/ramtest.c"
#include "southbridge/intel/i82371eb/i82371eb_enable_rom.c"
#include "southbridge/intel/i82371eb/i82371eb_early_smbus.c"
#include "northbridge/intel/i440bx/raminit.h"
#include "lib/debug.c"
#include "pc80/udelay_io.c"
#include "lib/delay.c"
-#include "cpu/x86/mtrr/earlymtrr.c"
#include "cpu/x86/bist.h"
#include "superio/winbond/w83977tf/w83977tf_early_serial.c"
+#include <lib.h>
#define SERIAL_DEV PNP_DEV(0x3f0, W83977TF_SP1)
@@ -47,11 +46,8 @@ static inline int spd_read_byte(unsigned int device, unsigned int address)
#include "northbridge/intel/i440bx/raminit.c"
#include "northbridge/intel/i440bx/debug.c"
-static void main(unsigned long bist)
+void main(unsigned long bist)
{
- if (bist == 0)
- early_mtrr_init();
-
w83977tf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
uart_init();
console_init();
@@ -61,10 +57,8 @@ static void main(unsigned long bist)
i82371eb_enable_rom(PCI_DEV(0, 7, 0)); /* ISA bridge is 00:07.0. */
enable_smbus();
- /* dump_spd_registers(); */
+ dump_spd_registers();
sdram_set_registers();
sdram_set_spd_registers();
sdram_enable();
- /* ram_check(0, 640 * 1024); */
}
-
diff --git a/src/mainboard/a-trend/atc-6240/Kconfig b/src/mainboard/a-trend/atc-6240/Kconfig
index 3d239ca082..6e07a372d4 100644
--- a/src/mainboard/a-trend/atc-6240/Kconfig
+++ b/src/mainboard/a-trend/atc-6240/Kconfig
@@ -25,7 +25,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select NORTHBRIDGE_INTEL_I440BX
select SOUTHBRIDGE_INTEL_I82371EB
select SUPERIO_WINBOND_W83627HF
- select ROMCC
select HAVE_PIRQ_TABLE
select UDELAY_TSC
select BOARD_ROMSIZE_KB_256
diff --git a/src/mainboard/a-trend/atc-6240/romstage.c b/src/mainboard/a-trend/atc-6240/romstage.c
index de4218be97..abfe3c4a15 100644
--- a/src/mainboard/a-trend/atc-6240/romstage.c
+++ b/src/mainboard/a-trend/atc-6240/romstage.c
@@ -26,16 +26,15 @@
#include <arch/romcc_io.h>
#include <arch/hlt.h>
#include <console/console.h>
-#include "lib/ramtest.c"
#include "southbridge/intel/i82371eb/i82371eb_enable_rom.c"
#include "southbridge/intel/i82371eb/i82371eb_early_smbus.c"
#include "northbridge/intel/i440bx/raminit.h"
#include "lib/debug.c"
#include "pc80/udelay_io.c"
#include "lib/delay.c"
-#include "cpu/x86/mtrr/earlymtrr.c"
#include "cpu/x86/bist.h"
#include "superio/winbond/w83627hf/w83627hf_early_serial.c"
+#include <lib.h>
#define SERIAL_DEV PNP_DEV(0x3f0, W83627HF_SP1)
@@ -47,11 +46,8 @@ static inline int spd_read_byte(unsigned int device, unsigned int address)
#include "northbridge/intel/i440bx/raminit.c"
#include "northbridge/intel/i440bx/debug.c"
-static void main(unsigned long bist)
+void main(unsigned long bist)
{
- if (bist == 0)
- early_mtrr_init();
-
w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
uart_init();
console_init();
@@ -61,10 +57,8 @@ static void main(unsigned long bist)
i82371eb_enable_rom(PCI_DEV(0, 7, 0)); /* ISA bridge is 00:07.0. */
enable_smbus();
- /* dump_spd_registers(); */
+ dump_spd_registers();
sdram_set_registers();
sdram_set_spd_registers();
sdram_enable();
- /* ram_check(0, 640 * 1024); */
}
-
diff --git a/src/mainboard/abit/be6-ii_v2_0/Kconfig b/src/mainboard/abit/be6-ii_v2_0/Kconfig
index 2ce99c128d..28a6086962 100644
--- a/src/mainboard/abit/be6-ii_v2_0/Kconfig
+++ b/src/mainboard/abit/be6-ii_v2_0/Kconfig
@@ -25,7 +25,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select NORTHBRIDGE_INTEL_I440BX
select SOUTHBRIDGE_INTEL_I82371EB
select SUPERIO_WINBOND_W83977TF
- select ROMCC
select HAVE_PIRQ_TABLE
select UDELAY_TSC
select BOARD_ROMSIZE_KB_256
diff --git a/src/mainboard/abit/be6-ii_v2_0/romstage.c b/src/mainboard/abit/be6-ii_v2_0/romstage.c
index 06c0d3e66a..d2cc87f892 100644
--- a/src/mainboard/abit/be6-ii_v2_0/romstage.c
+++ b/src/mainboard/abit/be6-ii_v2_0/romstage.c
@@ -26,17 +26,16 @@
#include <arch/romcc_io.h>
#include <arch/hlt.h>
#include <console/console.h>
-#include "lib/ramtest.c"
#include "southbridge/intel/i82371eb/i82371eb_enable_rom.c"
#include "southbridge/intel/i82371eb/i82371eb_early_smbus.c"
#include "northbridge/intel/i440bx/raminit.h"
#include "lib/debug.c"
#include "pc80/udelay_io.c"
#include "lib/delay.c"
-#include "cpu/x86/mtrr/earlymtrr.c"
#include "cpu/x86/bist.h"
/* FIXME: It's a Winbond W83977EF, actually. */
#include "superio/winbond/w83977tf/w83977tf_early_serial.c"
+#include <lib.h>
/* FIXME: It's a Winbond W83977EF, actually. */
#define SERIAL_DEV PNP_DEV(0x3f0, W83977TF_SP1)
@@ -49,11 +48,8 @@ static inline int spd_read_byte(unsigned int device, unsigned int address)
#include "northbridge/intel/i440bx/raminit.c"
#include "northbridge/intel/i440bx/debug.c"
-static void main(unsigned long bist)
+void main(unsigned long bist)
{
- if (bist == 0)
- early_mtrr_init();
-
/* FIXME: It's a Winbond W83977EF, actually. */
w83977tf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
uart_init();
@@ -64,10 +60,8 @@ static void main(unsigned long bist)
i82371eb_enable_rom(PCI_DEV(0, 7, 0)); /* ISA bridge at 00:07.0. */
enable_smbus();
- /* dump_spd_registers(); */
+ dump_spd_registers();
sdram_set_registers();
sdram_set_spd_registers();
sdram_enable();
- /* ram_check(0, 640 * 1024); */
}
-
diff --git a/src/mainboard/asus/p2b-d/Kconfig b/src/mainboard/asus/p2b-d/Kconfig
index a16debb29c..2643686ba4 100644
--- a/src/mainboard/asus/p2b-d/Kconfig
+++ b/src/mainboard/asus/p2b-d/Kconfig
@@ -25,7 +25,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select NORTHBRIDGE_INTEL_I440BX
select SOUTHBRIDGE_INTEL_I82371EB
select SUPERIO_WINBOND_W83977TF
- select ROMCC
select HAVE_PIRQ_TABLE
select HAVE_MP_TABLE
select SMP
diff --git a/src/mainboard/asus/p2b-d/romstage.c b/src/mainboard/asus/p2b-d/romstage.c
index 107bb68bfc..1264dd02cb 100644
--- a/src/mainboard/asus/p2b-d/romstage.c
+++ b/src/mainboard/asus/p2b-d/romstage.c
@@ -27,16 +27,15 @@
#include <stdlib.h>
#include <cpu/x86/lapic.h>
#include <console/console.h>
-#include "lib/ramtest.c"
#include "southbridge/intel/i82371eb/i82371eb_enable_rom.c"
#include "southbridge/intel/i82371eb/i82371eb_early_smbus.c"
#include "northbridge/intel/i440bx/raminit.h"
#include "lib/debug.c"
#include "pc80/udelay_io.c"
#include "lib/delay.c"
-#include "cpu/x86/mtrr/earlymtrr.c"
#include "cpu/x86/bist.h"
#include "superio/winbond/w83977tf/w83977tf_early_serial.c"
+#include <lib.h>
#define SERIAL_DEV PNP_DEV(0x3f0, W83977TF_SP1)
@@ -48,12 +47,9 @@ static inline int spd_read_byte(unsigned int device, unsigned int address)
#include "northbridge/intel/i440bx/raminit.c"
#include "northbridge/intel/i440bx/debug.c"
-static void main(unsigned long bist)
+void main(unsigned long bist)
{
- if (bist == 0) {
- early_mtrr_init();
- enable_lapic(); /* FIXME? */
- }
+ enable_lapic(); /* FIXME? */
w83977tf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
uart_init();
@@ -64,10 +60,8 @@ static void main(unsigned long bist)
i82371eb_enable_rom(PCI_DEV(0, 4, 0)); /* ISA bridge is 00:04.0. */
enable_smbus();
- /* dump_spd_registers(); */
+ dump_spd_registers();
sdram_set_registers();
sdram_set_spd_registers();
sdram_enable();
- /* ram_check(0, 640 * 1024); */
}
-
diff --git a/src/mainboard/asus/p2b-ds/Kconfig b/src/mainboard/asus/p2b-ds/Kconfig
index ff495d88b2..bdbcf34b4a 100644
--- a/src/mainboard/asus/p2b-ds/Kconfig
+++ b/src/mainboard/asus/p2b-ds/Kconfig
@@ -25,7 +25,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select NORTHBRIDGE_INTEL_I440BX
select SOUTHBRIDGE_INTEL_I82371EB
select SUPERIO_WINBOND_W83977TF
- select ROMCC
select HAVE_PIRQ_TABLE
select HAVE_MP_TABLE
select SMP
diff --git a/src/mainboard/asus/p2b-ds/romstage.c b/src/mainboard/asus/p2b-ds/romstage.c
index a68b8fa8fd..2bb1a46bbd 100644
--- a/src/mainboard/asus/p2b-ds/romstage.c
+++ b/src/mainboard/asus/p2b-ds/romstage.c
@@ -27,16 +27,15 @@
#include <stdlib.h>
#include <cpu/x86/lapic.h>
#include <console/console.h>
-#include "lib/ramtest.c"
#include "southbridge/intel/i82371eb/i82371eb_enable_rom.c"
#include "southbridge/intel/i82371eb/i82371eb_early_smbus.c"
#include "northbridge/intel/i440bx/raminit.h"
#include "lib/debug.c"
#include "pc80/udelay_io.c"
#include "lib/delay.c"
-#include "cpu/x86/mtrr/earlymtrr.c"
#include "cpu/x86/bist.h"
#include "superio/winbond/w83977tf/w83977tf_early_serial.c"
+#include <lib.h>
#define SERIAL_DEV PNP_DEV(0x3f0, W83977TF_SP1)
@@ -48,12 +47,9 @@ static inline int spd_read_byte(unsigned int device, unsigned int address)
#include "northbridge/intel/i440bx/raminit.c"
#include "northbridge/intel/i440bx/debug.c"
-static void main(unsigned long bist)
+void main(unsigned long bist)
{
- if (bist == 0) {
- early_mtrr_init();
- enable_lapic(); /* FIXME? */
- }
+ enable_lapic(); /* FIXME? */
w83977tf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
uart_init();
@@ -64,10 +60,8 @@ static void main(unsigned long bist)
i82371eb_enable_rom(PCI_DEV(0, 4, 0)); /* ISA bridge is 00:04.0. */
enable_smbus();
- /* dump_spd_registers(); */
+ dump_spd_registers();
sdram_set_registers();
sdram_set_spd_registers();
sdram_enable();
- /* ram_check(0, 640 * 1024); */
}
-
diff --git a/src/mainboard/asus/p2b-f/Kconfig b/src/mainboard/asus/p2b-f/Kconfig
index 8041031c41..2e17c04118 100644
--- a/src/mainboard/asus/p2b-f/Kconfig
+++ b/src/mainboard/asus/p2b-f/Kconfig
@@ -25,7 +25,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select NORTHBRIDGE_INTEL_I440BX
select SOUTHBRIDGE_INTEL_I82371EB
select SUPERIO_WINBOND_W83977TF
- select ROMCC
select HAVE_PIRQ_TABLE
select UDELAY_TSC
select BOARD_ROMSIZE_KB_256
diff --git a/src/mainboard/asus/p2b-f/romstage.c b/src/mainboard/asus/p2b-f/romstage.c
index e3cdf8c002..baf2db42c3 100644
--- a/src/mainboard/asus/p2b-f/romstage.c
+++ b/src/mainboard/asus/p2b-f/romstage.c
@@ -26,17 +26,16 @@
#include <arch/hlt.h>
#include <stdlib.h>
#include <console/console.h>
-#include "lib/ramtest.c"
#include "southbridge/intel/i82371eb/i82371eb_enable_rom.c"
#include "southbridge/intel/i82371eb/i82371eb_early_smbus.c"
#include "northbridge/intel/i440bx/raminit.h"
#include "lib/debug.c"
#include "pc80/udelay_io.c"
#include "lib/delay.c"
-#include "cpu/x86/mtrr/earlymtrr.c"
#include "cpu/x86/bist.h"
/* FIXME: The ASUS P2B-F has a Winbond W83977EF, actually. */
#include "superio/winbond/w83977tf/w83977tf_early_serial.c"
+#include <lib.h>
/* FIXME: The ASUS P2B-F has a Winbond W83977EF, actually. */
#define SERIAL_DEV PNP_DEV(0x3f0, W83977TF_SP1)
@@ -49,11 +48,8 @@ static inline int spd_read_byte(unsigned int device, unsigned int address)
#include "northbridge/intel/i440bx/raminit.c"
#include "northbridge/intel/i440bx/debug.c"
-static void main(unsigned long bist)
+void main(unsigned long bist)
{
- if (bist == 0)
- early_mtrr_init();
-
/* FIXME: The ASUS P2B-F has a Winbond W83977EF, actually. */
w83977tf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
uart_init();
@@ -64,10 +60,8 @@ static void main(unsigned long bist)
i82371eb_enable_rom(PCI_DEV(0, 4, 0)); /* ISA bridge is 00:04.0. */
enable_smbus();
- /* dump_spd_registers(); */
+ dump_spd_registers();
sdram_set_registers();
sdram_set_spd_registers();
sdram_enable();
- /* ram_check(0, 640 * 1024); */
}
-
diff --git a/src/mainboard/asus/p2b-ls/Kconfig b/src/mainboard/asus/p2b-ls/Kconfig
index 8afa739b2b..3b71879e48 100644
--- a/src/mainboard/asus/p2b-ls/Kconfig
+++ b/src/mainboard/asus/p2b-ls/Kconfig
@@ -25,7 +25,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select NORTHBRIDGE_INTEL_I440BX
select SOUTHBRIDGE_INTEL_I82371EB
select SUPERIO_WINBOND_W83977TF
- select ROMCC
select HAVE_PIRQ_TABLE
select UDELAY_TSC
select BOARD_ROMSIZE_KB_256
diff --git a/src/mainboard/asus/p2b-ls/romstage.c b/src/mainboard/asus/p2b-ls/romstage.c
index 77fdf62e6d..0b653a4a6b 100644
--- a/src/mainboard/asus/p2b-ls/romstage.c
+++ b/src/mainboard/asus/p2b-ls/romstage.c
@@ -26,17 +26,16 @@
#include <arch/hlt.h>
#include <stdlib.h>
#include <console/console.h>
-#include "lib/ramtest.c"
#include "southbridge/intel/i82371eb/i82371eb_enable_rom.c"
#include "southbridge/intel/i82371eb/i82371eb_early_smbus.c"
#include "northbridge/intel/i440bx/raminit.h"
#include "lib/debug.c"
#include "pc80/udelay_io.c"
#include "lib/delay.c"
-#include "cpu/x86/mtrr/earlymtrr.c"
#include "cpu/x86/bist.h"
/* FIXME: The ASUS P2B-LS has a Winbond W83977EF, actually. */
#include "superio/winbond/w83977tf/w83977tf_early_serial.c"
+#include <lib.h>
#define SERIAL_DEV PNP_DEV(0x3f0, W83977TF_SP1)
@@ -48,11 +47,8 @@ static inline int spd_read_byte(unsigned int device, unsigned int address)
#include "northbridge/intel/i440bx/raminit.c"
#include "northbridge/intel/i440bx/debug.c"
-static void main(unsigned long bist)
+void main(unsigned long bist)
{
- if (bist == 0)
- early_mtrr_init();
-
/* FIXME: The ASUS P2B-LS has a Winbond W83977EF, actually. */
w83977tf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
uart_init();
@@ -63,10 +59,8 @@ static void main(unsigned long bist)
i82371eb_enable_rom(PCI_DEV(0, 4, 0)); /* ISA bridge at 00:04.0. */
enable_smbus();
- /* dump_spd_registers(); */
+ dump_spd_registers();
sdram_set_registers();
sdram_set_spd_registers();
sdram_enable();
- /* ram_check(0, 640 * 1024); */
}
-
diff --git a/src/mainboard/asus/p2b/Kconfig b/src/mainboard/asus/p2b/Kconfig
index 240820691c..cb1c8507e3 100644
--- a/src/mainboard/asus/p2b/Kconfig
+++ b/src/mainboard/asus/p2b/Kconfig
@@ -25,7 +25,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select NORTHBRIDGE_INTEL_I440BX
select SOUTHBRIDGE_INTEL_I82371EB
select SUPERIO_WINBOND_W83977TF
- select ROMCC
select HAVE_PIRQ_TABLE
select UDELAY_TSC
select BOARD_ROMSIZE_KB_256
diff --git a/src/mainboard/asus/p2b/romstage.c b/src/mainboard/asus/p2b/romstage.c
index e57f9755c0..e3a48b3b61 100644
--- a/src/mainboard/asus/p2b/romstage.c
+++ b/src/mainboard/asus/p2b/romstage.c
@@ -26,16 +26,15 @@
#include <arch/hlt.h>
#include <stdlib.h>
#include <console/console.h>
-#include "lib/ramtest.c"
#include "southbridge/intel/i82371eb/i82371eb_enable_rom.c"
#include "southbridge/intel/i82371eb/i82371eb_early_smbus.c"
#include "northbridge/intel/i440bx/raminit.h"
#include "lib/debug.c"
#include "pc80/udelay_io.c"
#include "lib/delay.c"
-#include "cpu/x86/mtrr/earlymtrr.c"
#include "cpu/x86/bist.h"
#include "superio/winbond/w83977tf/w83977tf_early_serial.c"
+#include <lib.h>
#define SERIAL_DEV PNP_DEV(0x3f0, W83977TF_SP1)
@@ -47,11 +46,8 @@ static inline int spd_read_byte(unsigned int device, unsigned int address)
#include "northbridge/intel/i440bx/raminit.c"
#include "northbridge/intel/i440bx/debug.c"
-static void main(unsigned long bist)
+void main(unsigned long bist)
{
- if (bist == 0)
- early_mtrr_init();
-
w83977tf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
uart_init();
console_init();
@@ -61,10 +57,8 @@ static void main(unsigned long bist)
i82371eb_enable_rom(PCI_DEV(0, 4, 0)); /* ISA bridge at 00:04.0. */
enable_smbus();
- /* dump_spd_registers(); */
+ dump_spd_registers();
sdram_set_registers();
sdram_set_spd_registers();
sdram_enable();
- /* ram_check(0, 640 * 1024); */
}
-
diff --git a/src/mainboard/asus/p3b-f/Kconfig b/src/mainboard/asus/p3b-f/Kconfig
index 6581a94fb1..8c8ea0f63e 100644
--- a/src/mainboard/asus/p3b-f/Kconfig
+++ b/src/mainboard/asus/p3b-f/Kconfig
@@ -25,7 +25,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select NORTHBRIDGE_INTEL_I440BX
select SOUTHBRIDGE_INTEL_I82371EB
select SUPERIO_WINBOND_W83977TF
- select ROMCC
select HAVE_PIRQ_TABLE
select UDELAY_TSC
select BOARD_ROMSIZE_KB_256
diff --git a/src/mainboard/asus/p3b-f/romstage.c b/src/mainboard/asus/p3b-f/romstage.c
index cde5400ff4..31b401ac96 100644
--- a/src/mainboard/asus/p3b-f/romstage.c
+++ b/src/mainboard/asus/p3b-f/romstage.c
@@ -26,7 +26,6 @@
#include <arch/hlt.h>
#include <stdlib.h>
#include <console/console.h>
-#include "lib/ramtest.c"
#include "southbridge/intel/i82371eb/i82371eb_enable_rom.c"
#include "southbridge/intel/i82371eb/i82371eb_early_smbus.c"
#include "southbridge/intel/i82371eb/i82371eb_early_pm.c"
@@ -34,10 +33,10 @@
#include "lib/debug.c"
#include "pc80/udelay_io.c"
#include "lib/delay.c"
-#include "cpu/x86/mtrr/earlymtrr.c"
#include "cpu/x86/bist.h"
/* FIXME: The ASUS P3B-F has a Winbond W83977EF, actually. */
#include "superio/winbond/w83977tf/w83977tf_early_serial.c"
+#include <lib.h>
/* FIXME: The ASUS P3B-F has a Winbond W83977EF, actually. */
#define SERIAL_DEV PNP_DEV(0x3f0, W83977TF_SP1)
@@ -81,11 +80,8 @@ static void disable_spd(void)
outb(0x67, PM_IO_BASE + 0x37);
}
-static void main(unsigned long bist)
+void main(unsigned long bist)
{
- if (bist == 0)
- early_mtrr_init();
-
/* FIXME: The ASUS P3B-F has a Winbond W83977EF, actually. */
w83977tf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
uart_init();
@@ -100,12 +96,10 @@ static void main(unsigned long bist)
enable_spd();
- /* dump_spd_registers(); */
+ dump_spd_registers();
sdram_set_registers();
sdram_set_spd_registers();
sdram_enable();
- /* ram_check(0, 640 * 1024); */
disable_spd();
}
-
diff --git a/src/mainboard/azza/pt-6ibd/Kconfig b/src/mainboard/azza/pt-6ibd/Kconfig
index 2d4aecf450..1d11c0fee0 100644
--- a/src/mainboard/azza/pt-6ibd/Kconfig
+++ b/src/mainboard/azza/pt-6ibd/Kconfig
@@ -25,7 +25,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select NORTHBRIDGE_INTEL_I440BX
select SOUTHBRIDGE_INTEL_I82371EB
select SUPERIO_WINBOND_W83977TF
- select ROMCC
select HAVE_PIRQ_TABLE
select UDELAY_TSC
select BOARD_ROMSIZE_KB_256
diff --git a/src/mainboard/azza/pt-6ibd/romstage.c b/src/mainboard/azza/pt-6ibd/romstage.c
index a195622b87..a901c38541 100644
--- a/src/mainboard/azza/pt-6ibd/romstage.c
+++ b/src/mainboard/azza/pt-6ibd/romstage.c
@@ -26,17 +26,16 @@
#include <arch/hlt.h>
#include <stdlib.h>
#include <console/console.h>
-#include "lib/ramtest.c"
#include "southbridge/intel/i82371eb/i82371eb_enable_rom.c"
#include "southbridge/intel/i82371eb/i82371eb_early_smbus.c"
#include "northbridge/intel/i440bx/raminit.h"
#include "lib/debug.c"
#include "pc80/udelay_io.c"
#include "lib/delay.c"
-#include "cpu/x86/mtrr/earlymtrr.c"
#include "cpu/x86/bist.h"
/* FIXME: It's a Winbond W83977EF, actually. */
#include "superio/winbond/w83977tf/w83977tf_early_serial.c"
+#include <lib.h>
/* FIXME: It's a Winbond W83977EF, actually. */
#define SERIAL_DEV PNP_DEV(0x3f0, W83977TF_SP1)
@@ -49,11 +48,8 @@ static inline int spd_read_byte(unsigned int device, unsigned int address)
#include "northbridge/intel/i440bx/raminit.c"
#include "northbridge/intel/i440bx/debug.c"
-static void main(unsigned long bist)
+void main(unsigned long bist)
{
- if (bist == 0)
- early_mtrr_init();
-
/* FIXME: It's a Winbond W83977EF, actually. */
w83977tf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
uart_init();
@@ -64,10 +60,8 @@ static void main(unsigned long bist)
i82371eb_enable_rom(PCI_DEV(0, 7, 0)); /* ISA bridge is 00:07.0. */
enable_smbus();
- /* dump_spd_registers(); */
+ dump_spd_registers();
sdram_set_registers();
sdram_set_spd_registers();
sdram_enable();
- /* ram_check(0, 640 * 1024); */
}
-
diff --git a/src/mainboard/biostar/m6tba/Kconfig b/src/mainboard/biostar/m6tba/Kconfig
index f9129f4b54..524dd78ca2 100644
--- a/src/mainboard/biostar/m6tba/Kconfig
+++ b/src/mainboard/biostar/m6tba/Kconfig
@@ -25,7 +25,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select NORTHBRIDGE_INTEL_I440BX
select SOUTHBRIDGE_INTEL_I82371EB
select SUPERIO_SMSC_SMSCSUPERIO
- select ROMCC
select HAVE_PIRQ_TABLE
select UDELAY_TSC
select BOARD_ROMSIZE_KB_256
diff --git a/src/mainboard/biostar/m6tba/romstage.c b/src/mainboard/biostar/m6tba/romstage.c
index fa7f7093a5..fb60168036 100644
--- a/src/mainboard/biostar/m6tba/romstage.c
+++ b/src/mainboard/biostar/m6tba/romstage.c
@@ -26,16 +26,15 @@
#include <arch/hlt.h>
#include <stdlib.h>
#include <console/console.h>
-#include "lib/ramtest.c"
#include "southbridge/intel/i82371eb/i82371eb_enable_rom.c"
#include "southbridge/intel/i82371eb/i82371eb_early_smbus.c"
#include "northbridge/intel/i440bx/raminit.h"
#include "lib/debug.c"
#include "pc80/udelay_io.c"
#include "lib/delay.c"
-#include "cpu/x86/mtrr/earlymtrr.c"
#include "cpu/x86/bist.h"
#include "superio/smsc/smscsuperio/smscsuperio_early_serial.c"
+#include <lib.h>
#define SERIAL_DEV PNP_DEV(0x3f0, SMSCSUPERIO_SP1)
@@ -47,11 +46,8 @@ static inline int spd_read_byte(unsigned int device, unsigned int address)
#include "northbridge/intel/i440bx/raminit.c"
#include "northbridge/intel/i440bx/debug.c"
-static void main(unsigned long bist)
+void main(unsigned long bist)
{
- if (bist == 0)
- early_mtrr_init();
-
smscsuperio_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
uart_init();
console_init();
@@ -61,10 +57,8 @@ static void main(unsigned long bist)
/* Enable access to the full ROM chip, needed very early by CBFS. */
i82371eb_enable_rom(PCI_DEV(0, 7, 0)); /* ISA bridge is 00:07.0. */
- /* dump_spd_registers(); */
+ dump_spd_registers();
sdram_set_registers();
sdram_set_spd_registers();
sdram_enable();
- /* ram_check(0, 640 * 1024); */
}
-
diff --git a/src/mainboard/compaq/deskpro_en_sff_p600/Kconfig b/src/mainboard/compaq/deskpro_en_sff_p600/Kconfig
index c59577e25d..715c244bd6 100644
--- a/src/mainboard/compaq/deskpro_en_sff_p600/Kconfig
+++ b/src/mainboard/compaq/deskpro_en_sff_p600/Kconfig
@@ -26,7 +26,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select SOUTHBRIDGE_INTEL_I82371EB
# should be SUPERIO_NSC_PC97307!
select SUPERIO_NSC_PC97317
- select ROMCC
select HAVE_PIRQ_TABLE
select UDELAY_TSC
select BOARD_ROMSIZE_KB_256
diff --git a/src/mainboard/compaq/deskpro_en_sff_p600/romstage.c b/src/mainboard/compaq/deskpro_en_sff_p600/romstage.c
index 000198f908..42c43c86cf 100644
--- a/src/mainboard/compaq/deskpro_en_sff_p600/romstage.c
+++ b/src/mainboard/compaq/deskpro_en_sff_p600/romstage.c
@@ -26,17 +26,16 @@
#include <arch/hlt.h>
#include <stdlib.h>
#include <console/console.h>
-#include "lib/ramtest.c"
#include "southbridge/intel/i82371eb/i82371eb_enable_rom.c"
#include "southbridge/intel/i82371eb/i82371eb_early_smbus.c"
#include "northbridge/intel/i440bx/raminit.h"
#include "lib/debug.c"
#include "pc80/udelay_io.c"
#include "lib/delay.c"
-#include "cpu/x86/mtrr/earlymtrr.c"
#include "cpu/x86/bist.h"
/* FIXME: This should be PC97307 (but it's buggy at the moment)! */
#include "superio/nsc/pc97317/pc97317_early_serial.c"
+#include <lib.h>
/* FIXME: This should be PC97307 (but it's buggy at the moment)! */
#define SERIAL_DEV PNP_DEV(0x15c, PC97317_SP1)
@@ -49,11 +48,8 @@ static inline int spd_read_byte(unsigned int device, unsigned int address)
#include "northbridge/intel/i440bx/raminit.c"
#include "northbridge/intel/i440bx/debug.c"
-static void main(unsigned long bist)
+void main(unsigned long bist)
{
- if (bist == 0)
- early_mtrr_init();
-
/* FIXME: Should be PC97307! */
pc97317_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
uart_init();
@@ -64,10 +60,8 @@ static void main(unsigned long bist)
i82371eb_enable_rom(PCI_DEV(0, 14, 0)); /* ISA bridge is 00:14.0. */
enable_smbus();
- /* dump_spd_registers(); */
+ dump_spd_registers();
sdram_set_registers();
sdram_set_spd_registers();
sdram_enable();
- /* ram_check(0, 640 * 1024); */
}
-
diff --git a/src/mainboard/gigabyte/ga-6bxc/Kconfig b/src/mainboard/gigabyte/ga-6bxc/Kconfig
index f89c44088f..04b73d1876 100644
--- a/src/mainboard/gigabyte/ga-6bxc/Kconfig
+++ b/src/mainboard/gigabyte/ga-6bxc/Kconfig
@@ -25,7 +25,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select NORTHBRIDGE_INTEL_I440BX
select SOUTHBRIDGE_INTEL_I82371EB
select SUPERIO_ITE_IT8671F
- select ROMCC
select HAVE_PIRQ_TABLE
select UDELAY_TSC
select BOARD_ROMSIZE_KB_256
diff --git a/src/mainboard/gigabyte/ga-6bxc/romstage.c b/src/mainboard/gigabyte/ga-6bxc/romstage.c
index 1f58a0031b..040e762d24 100644
--- a/src/mainboard/gigabyte/ga-6bxc/romstage.c
+++ b/src/mainboard/gigabyte/ga-6bxc/romstage.c
@@ -26,16 +26,16 @@
#include <arch/hlt.h>
#include <stdlib.h>
#include <console/console.h>
-#include "lib/ramtest.c"
#include "southbridge/intel/i82371eb/i82371eb_enable_rom.c"
#include "southbridge/intel/i82371eb/i82371eb_early_smbus.c"
#include "northbridge/intel/i440bx/raminit.h"
#include "lib/debug.c"
#include "pc80/udelay_io.c"
#include "lib/delay.c"
-#include "cpu/x86/mtrr/earlymtrr.c"
#include "cpu/x86/bist.h"
+void it8671f_48mhz_clkin(void);
#include "superio/ite/it8671f/it8671f_early_serial.c"
+#include <lib.h>
#define SERIAL_DEV PNP_DEV(0x3f0, IT8671F_SP1)
@@ -47,11 +47,8 @@ static inline int spd_read_byte(unsigned int device, unsigned int address)
#include "northbridge/intel/i440bx/raminit.c"
#include "northbridge/intel/i440bx/debug.c"
-static void main(unsigned long bist)
+void main(unsigned long bist)
{
- if (bist == 0)
- early_mtrr_init();
-
it8671f_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
uart_init();
console_init();
@@ -61,10 +58,8 @@ static void main(unsigned long bist)
i82371eb_enable_rom(PCI_DEV(0, 7, 0)); /* ISA bridge is 00:07.0. */
enable_smbus();
- /* dump_spd_registers(); */
+ dump_spd_registers();
sdram_set_registers();
sdram_set_spd_registers();
sdram_enable();
- /* ram_check(0, 640 * 1024); */
}
-
diff --git a/src/mainboard/gigabyte/ga-6bxe/Kconfig b/src/mainboard/gigabyte/ga-6bxe/Kconfig
index 34a3281d78..e49dc1d4a7 100644
--- a/src/mainboard/gigabyte/ga-6bxe/Kconfig
+++ b/src/mainboard/gigabyte/ga-6bxe/Kconfig
@@ -26,7 +26,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select NORTHBRIDGE_INTEL_I440BX
select SOUTHBRIDGE_INTEL_I82371EB
select SUPERIO_ITE_IT8671F
- select ROMCC
select HAVE_PIRQ_TABLE
select UDELAY_TSC
select BOARD_ROMSIZE_KB_256
diff --git a/src/mainboard/gigabyte/ga-6bxe/romstage.c b/src/mainboard/gigabyte/ga-6bxe/romstage.c
index f9b5135402..aafd39453c 100644
--- a/src/mainboard/gigabyte/ga-6bxe/romstage.c
+++ b/src/mainboard/gigabyte/ga-6bxe/romstage.c
@@ -26,16 +26,16 @@
#include <arch/hlt.h>
#include <stdlib.h>
#include <console/console.h>
-#include "lib/ramtest.c"
#include "southbridge/intel/i82371eb/i82371eb_enable_rom.c"
#include "southbridge/intel/i82371eb/i82371eb_early_smbus.c"
#include "northbridge/intel/i440bx/raminit.h"
#include "lib/debug.c"
#include "pc80/udelay_io.c"
#include "lib/delay.c"
-#include "cpu/x86/mtrr/earlymtrr.c"
#include "cpu/x86/bist.h"
+static void it8671f_48mhz_clkin(void);
#include "superio/ite/it8671f/it8671f_early_serial.c"
+#include <lib.h>
#define SERIAL_DEV PNP_DEV(0x3f0, IT8671F_SP1)
@@ -47,11 +47,8 @@ static inline int spd_read_byte(unsigned int device, unsigned int address)
#include "northbridge/intel/i440bx/raminit.c"
#include "northbridge/intel/i440bx/debug.c"
-static void main(unsigned long bist)
+void main(unsigned long bist)
{
- if (bist == 0)
- early_mtrr_init();
-
it8671f_48mhz_clkin();
it8671f_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
uart_init();
@@ -62,9 +59,8 @@ static void main(unsigned long bist)
i82371eb_enable_rom(PCI_DEV(0, 7, 0)); /* ISA bridge is 00:07.0. */
enable_smbus();
- /* dump_spd_registers(); */
+ dump_spd_registers();
sdram_set_registers();
sdram_set_spd_registers();
sdram_enable();
- /* ram_check(0, 640 * 1024); */
}
diff --git a/src/mainboard/msi/ms6119/Kconfig b/src/mainboard/msi/ms6119/Kconfig
index a11f9cf338..b9a585e209 100644
--- a/src/mainboard/msi/ms6119/Kconfig
+++ b/src/mainboard/msi/ms6119/Kconfig
@@ -25,7 +25,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select NORTHBRIDGE_INTEL_I440BX
select SOUTHBRIDGE_INTEL_I82371EB
select SUPERIO_WINBOND_W83977TF
- select ROMCC
select HAVE_PIRQ_TABLE
select UDELAY_TSC
select BOARD_ROMSIZE_KB_256
diff --git a/src/mainboard/msi/ms6119/romstage.c b/src/mainboard/msi/ms6119/romstage.c
index 77e64a60d5..aaa03ee52d 100644
--- a/src/mainboard/msi/ms6119/romstage.c
+++ b/src/mainboard/msi/ms6119/romstage.c
@@ -26,16 +26,15 @@
#include <arch/romcc_io.h>
#include <arch/hlt.h>
#include <console/console.h>
-#include "lib/ramtest.c"
#include "southbridge/intel/i82371eb/i82371eb_enable_rom.c"
#include "southbridge/intel/i82371eb/i82371eb_early_smbus.c"
#include "northbridge/intel/i440bx/raminit.h"
#include "lib/debug.c"
#include "pc80/udelay_io.c"
#include "lib/delay.c"
-#include "cpu/x86/mtrr/earlymtrr.c"
#include "cpu/x86/bist.h"
#include "superio/winbond/w83977tf/w83977tf_early_serial.c"
+#include <lib.h>
#define SERIAL_DEV PNP_DEV(0x3f0, W83977TF_SP1)
@@ -47,11 +46,8 @@ static inline int spd_read_byte(unsigned int device, unsigned int address)
#include "northbridge/intel/i440bx/raminit.c"
#include "northbridge/intel/i440bx/debug.c"
-static void main(unsigned long bist)
+void main(unsigned long bist)
{
- if (bist == 0)
- early_mtrr_init();
-
w83977tf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
uart_init();
console_init();
@@ -61,10 +57,8 @@ static void main(unsigned long bist)
i82371eb_enable_rom(PCI_DEV(0, 7, 0)); /* ISA bridge is 00:07.0. */
enable_smbus();
- /* dump_spd_registers(); */
+ dump_spd_registers();
sdram_set_registers();
sdram_set_spd_registers();
sdram_enable();
- /* ram_check(0, 640 * 1024); */
}
-
diff --git a/src/mainboard/msi/ms6147/Kconfig b/src/mainboard/msi/ms6147/Kconfig
index 198618f974..f126a6f08f 100644
--- a/src/mainboard/msi/ms6147/Kconfig
+++ b/src/mainboard/msi/ms6147/Kconfig
@@ -25,7 +25,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select NORTHBRIDGE_INTEL_I440BX
select SOUTHBRIDGE_INTEL_I82371EB
select SUPERIO_WINBOND_W83977TF
- select ROMCC
select HAVE_PIRQ_TABLE
select UDELAY_TSC
select BOARD_ROMSIZE_KB_256
diff --git a/src/mainboard/msi/ms6147/romstage.c b/src/mainboard/msi/ms6147/romstage.c
index bcf5725f9b..2f84fbffd6 100644
--- a/src/mainboard/msi/ms6147/romstage.c
+++ b/src/mainboard/msi/ms6147/romstage.c
@@ -26,16 +26,15 @@
#include <arch/romcc_io.h>
#include <arch/hlt.h>
#include <console/console.h>
-#include "lib/ramtest.c"
#include "southbridge/intel/i82371eb/i82371eb_enable_rom.c"
#include "southbridge/intel/i82371eb/i82371eb_early_smbus.c"
#include "northbridge/intel/i440bx/raminit.h"
#include "lib/debug.c"
#include "pc80/udelay_io.c"
#include "lib/delay.c"
-#include "cpu/x86/mtrr/earlymtrr.c"
#include <cpu/x86/bist.h>
#include "superio/winbond/w83977tf/w83977tf_early_serial.c"
+#include <lib.h>
#define SERIAL_DEV PNP_DEV(0x3f0, W83977TF_SP1)
@@ -45,13 +44,10 @@ static inline int spd_read_byte(unsigned int device, unsigned int address)
}
#include "northbridge/intel/i440bx/raminit.c"
-/* #include "northbridge/intel/i440bx/debug.c" */
+#include "northbridge/intel/i440bx/debug.c"
-static void main(unsigned long bist)
+void main(unsigned long bist)
{
- if (bist == 0)
- early_mtrr_init();
-
w83977tf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
uart_init();
console_init();
@@ -61,17 +57,8 @@ static void main(unsigned long bist)
i82371eb_enable_rom(PCI_DEV(0, 7, 0)); /* ISA bridge is 00:07.0. */
enable_smbus();
- /* dump_spd_registers(); */
+ dump_spd_registers();
sdram_set_registers();
sdram_set_spd_registers();
sdram_enable();
-#if 0
- ram_check(0, 640 * 1024); /* DOS-area */
- ram_check(0x00100000, 0x00400000); /* 1MB to 4MB */
- ram_check(0x00100000, 0x03ffffff); /* 1MB to 64MB- */
- ram_check(0x03fff000, 0x04000010); /* Across 64MB boundary */
- ram_check(0x07ffff00, 0x07fffff0); /* Just below 128MB */
- ram_check(0x00100000, 0x07ffffff); /* 1MB to 128MB- */
-#endif
}
-
diff --git a/src/mainboard/msi/ms6156/Kconfig b/src/mainboard/msi/ms6156/Kconfig
index ba132650ed..a5a4a083bd 100644
--- a/src/mainboard/msi/ms6156/Kconfig
+++ b/src/mainboard/msi/ms6156/Kconfig
@@ -25,7 +25,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select NORTHBRIDGE_INTEL_I440BX
select SOUTHBRIDGE_INTEL_I82371EB
select SUPERIO_WINBOND_W83977TF
- select ROMCC
select HAVE_PIRQ_TABLE
select UDELAY_TSC
select BOARD_ROMSIZE_KB_256
diff --git a/src/mainboard/msi/ms6156/romstage.c b/src/mainboard/msi/ms6156/romstage.c
index 49e7964cec..45c97eea6a 100644
--- a/src/mainboard/msi/ms6156/romstage.c
+++ b/src/mainboard/msi/ms6156/romstage.c
@@ -26,16 +26,15 @@
#include <arch/romcc_io.h>
#include <arch/hlt.h>
#include <console/console.h>
-#include "lib/ramtest.c"
#include "southbridge/intel/i82371eb/i82371eb_enable_rom.c"
#include "southbridge/intel/i82371eb/i82371eb_early_smbus.c"
#include "northbridge/intel/i440bx/raminit.h"
#include "lib/debug.c"
#include "pc80/udelay_io.c"
#include "lib/delay.c"
-#include "cpu/x86/mtrr/earlymtrr.c"
#include "cpu/x86/bist.h"
#include "superio/winbond/w83977tf/w83977tf_early_serial.c"
+#include <lib.h>
#define SERIAL_DEV PNP_DEV(0x3f0, W83977TF_SP1)
@@ -47,11 +46,8 @@ static inline int spd_read_byte(unsigned int device, unsigned int address)
#include "northbridge/intel/i440bx/raminit.c"
#include "northbridge/intel/i440bx/debug.c"
-static void main(unsigned long bist)
+void main(unsigned long bist)
{
- if (bist == 0)
- early_mtrr_init();
-
w83977tf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
uart_init();
console_init();
@@ -61,10 +57,8 @@ static void main(unsigned long bist)
i82371eb_enable_rom(PCI_DEV(0, 7, 0)); /* ISA bridge is 00:07.0. */
enable_smbus();
- /* dump_spd_registers(); */
+ dump_spd_registers();
sdram_set_registers();
sdram_set_spd_registers();
sdram_enable();
- /* ram_check(0, 640 * 1024); */
}
-
diff --git a/src/mainboard/nokia/ip530/romstage.c b/src/mainboard/nokia/ip530/romstage.c
index 8de76d8129..57d3dede86 100644
--- a/src/mainboard/nokia/ip530/romstage.c
+++ b/src/mainboard/nokia/ip530/romstage.c
@@ -26,16 +26,15 @@
#include <arch/hlt.h>
#include <stdlib.h>
#include <console/console.h>
-#include "lib/ramtest.c"
#include "southbridge/intel/i82371eb/i82371eb_enable_rom.c"
#include "southbridge/intel/i82371eb/i82371eb_early_smbus.c"
#include "northbridge/intel/i440bx/raminit.h"
#include "lib/debug.c"
#include "pc80/udelay_io.c"
#include "lib/delay.c"
-#include "cpu/x86/mtrr/earlymtrr.c"
#include "cpu/x86/bist.h"
#include "superio/smsc/smscsuperio/smscsuperio_early_serial.c"
+#include <lib.h>
#define SERIAL_DEV PNP_DEV(0x3f0, SMSCSUPERIO_SP1)
@@ -47,11 +46,8 @@ static inline int spd_read_byte(unsigned int device, unsigned int address)
#include "northbridge/intel/i440bx/raminit.c"
#include "northbridge/intel/i440bx/debug.c"
-static void main(unsigned long bist)
+void main(unsigned long bist)
{
- if (bist == 0)
- early_mtrr_init();
-
smscsuperio_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
uart_init();
console_init();
@@ -61,9 +57,8 @@ static void main(unsigned long bist)
i82371eb_enable_rom(PCI_DEV(0, 7, 0) ); /* ISA bridge at 00:07.0. */
enable_smbus();
- /* dump_spd_registers(); */
+ dump_spd_registers();
sdram_set_registers();
sdram_set_spd_registers();
sdram_enable();
- /* ram_check(0, 640 * 1024); */
}
diff --git a/src/mainboard/soyo/sy-6ba-plus-iii/Kconfig b/src/mainboard/soyo/sy-6ba-plus-iii/Kconfig
index bff1bdbc12..d873e1fc3c 100644
--- a/src/mainboard/soyo/sy-6ba-plus-iii/Kconfig
+++ b/src/mainboard/soyo/sy-6ba-plus-iii/Kconfig
@@ -25,7 +25,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select NORTHBRIDGE_INTEL_I440BX
select SOUTHBRIDGE_INTEL_I82371EB
select SUPERIO_ITE_IT8671F
- select ROMCC
select HAVE_PIRQ_TABLE
select UDELAY_TSC
select BOARD_ROMSIZE_KB_256
diff --git a/src/mainboard/soyo/sy-6ba-plus-iii/romstage.c b/src/mainboard/soyo/sy-6ba-plus-iii/romstage.c
index cd5289d414..901d271656 100644
--- a/src/mainboard/soyo/sy-6ba-plus-iii/romstage.c
+++ b/src/mainboard/soyo/sy-6ba-plus-iii/romstage.c
@@ -26,16 +26,16 @@
#include <arch/hlt.h>
#include <stdlib.h>
#include <console/console.h>
-#include "lib/ramtest.c"
#include "southbridge/intel/i82371eb/i82371eb_enable_rom.c"
#include "southbridge/intel/i82371eb/i82371eb_early_smbus.c"
#include "northbridge/intel/i440bx/raminit.h"
#include "lib/debug.c"
#include "pc80/udelay_io.c"
#include "lib/delay.c"
-#include "cpu/x86/mtrr/earlymtrr.c"
#include "cpu/x86/bist.h"
+void it8671f_48mhz_clkin(void);
#include "superio/ite/it8671f/it8671f_early_serial.c"
+#include <lib.h>
#define SERIAL_DEV PNP_DEV(0x370, IT8671F_SP1)
@@ -47,11 +47,8 @@ static inline int spd_read_byte(unsigned int device, unsigned int address)
#include "northbridge/intel/i440bx/raminit.c"
#include "northbridge/intel/i440bx/debug.c"
-static void main(unsigned long bist)
+void main(unsigned long bist)
{
- if (bist == 0)
- early_mtrr_init();
-
it8671f_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
uart_init();
console_init();
@@ -61,10 +58,8 @@ static void main(unsigned long bist)
i82371eb_enable_rom(PCI_DEV(0, 7, 0)); /* ISA bridge is 00:07.0. */
enable_smbus();
- /* dump_spd_registers(); */
+ dump_spd_registers();
sdram_set_registers();
sdram_set_spd_registers();
sdram_enable();
- /* ram_check(0, 640 * 1024); */
}
-
diff --git a/src/mainboard/tyan/s1846/Kconfig b/src/mainboard/tyan/s1846/Kconfig
index cd64746b53..ec6ea76479 100644
--- a/src/mainboard/tyan/s1846/Kconfig
+++ b/src/mainboard/tyan/s1846/Kconfig
@@ -25,7 +25,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select NORTHBRIDGE_INTEL_I440BX
select SOUTHBRIDGE_INTEL_I82371EB
select SUPERIO_NSC_PC87309
- select ROMCC
select UDELAY_TSC
select BOARD_ROMSIZE_KB_256
diff --git a/src/mainboard/tyan/s1846/romstage.c b/src/mainboard/tyan/s1846/romstage.c
index 3a0e0b2755..8b9ae8db14 100644
--- a/src/mainboard/tyan/s1846/romstage.c
+++ b/src/mainboard/tyan/s1846/romstage.c
@@ -26,16 +26,15 @@
#include <arch/hlt.h>
#include <stdlib.h>
#include <console/console.h>
-#include "lib/ramtest.c"
#include "southbridge/intel/i82371eb/i82371eb_enable_rom.c"
#include "southbridge/intel/i82371eb/i82371eb_early_smbus.c"
#include "northbridge/intel/i440bx/raminit.h"
#include "lib/debug.c"
#include "pc80/udelay_io.c"
#include "lib/delay.c"
-#include "cpu/x86/mtrr/earlymtrr.c"
#include "cpu/x86/bist.h"
#include "superio/nsc/pc87309/pc87309_early_serial.c"
+#include <lib.h>
#define SERIAL_DEV PNP_DEV(0x2e, PC87309_SP1)
@@ -47,11 +46,8 @@ static inline int spd_read_byte(unsigned int device, unsigned int address)
#include "northbridge/intel/i440bx/raminit.c"
#include "northbridge/intel/i440bx/debug.c"
-static void main(unsigned long bist)
+void main(unsigned long bist)
{
- if (bist == 0)
- early_mtrr_init();
-
pc87309_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
uart_init();
console_init();
@@ -61,10 +57,8 @@ static void main(unsigned long bist)
i82371eb_enable_rom(PCI_DEV(0, 7, 0)); /* ISA bridge is 00:07.0. */
enable_smbus();
- /* dump_spd_registers(); */
+ dump_spd_registers();
sdram_set_registers();
sdram_set_spd_registers();
sdram_enable();
- /* ram_check(0, 640 * 1024); */
}
-