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authorEdward O'Callaghan <eocallaghan@alterapraxis.com>2014-05-26 04:03:24 +1000
committerKyösti Mälkki <kyosti.malkki@gmail.com>2014-05-31 21:16:39 +0200
commit9068788a8f0c96a5153fcd4e5ed80eac80b060c6 (patch)
tree7196cf65855fd158c28a19d53413142a6feedb17 /src/mainboard
parent3c3e34d69fe4b185d4c0b698dfc6fcbf11b50dbb (diff)
downloadcoreboot-9068788a8f0c96a5153fcd4e5ed80eac80b060c6.tar.xz
superio/winbond/w83627ehg: Depreciate romstage component
Part 1/2: These are actually not necessary if Super I/O support is properly utilized. Change-Id: I39b621e582f8d0762276d29492c91dce500f0665 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5870 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Diffstat (limited to 'src/mainboard')
-rw-r--r--src/mainboard/nvidia/l1_2pvv/romstage.c3
1 files changed, 2 insertions, 1 deletions
diff --git a/src/mainboard/nvidia/l1_2pvv/romstage.c b/src/mainboard/nvidia/l1_2pvv/romstage.c
index d411354428..df78a0c622 100644
--- a/src/mainboard/nvidia/l1_2pvv/romstage.c
+++ b/src/mainboard/nvidia/l1_2pvv/romstage.c
@@ -36,6 +36,7 @@
#include "lib/delay.c"
#include "cpu/x86/lapic.h"
#include "northbridge/amd/amdk8/reset_test.c"
+#include <superio/winbond/common/winbond.h>
#include <superio/winbond/w83627ehg/w83627ehg.h>
#include "cpu/x86/bist.h"
#include "northbridge/amd/amdk8/debug.c"
@@ -119,11 +120,11 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
pnp_enter_ext_func_mode(SERIAL_DEV);
pnp_write_config(SERIAL_DEV, 0x24, 0);
- w83627ehg_enable_dev(SERIAL_DEV, CONFIG_TTYS0_BASE);
pnp_exit_ext_func_mode(SERIAL_DEV);
setup_mb_resource_map();
+ winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
console_init();
/* Halt if there was a built in self test failure */