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authorTim Wawrzynczak <twawrzynczak@chromium.org>2019-07-10 09:13:55 -0600
committerMartin Roth <martinroth@google.com>2019-07-11 15:03:09 +0000
commitc5651568ea63aedc92669c5447c0c9755e726244 (patch)
tree29f7924fd05618321471199b5806a7c241387849 /src/mainboard
parenta17242577add6dfd54d1ff8d0e46958b758e3718 (diff)
downloadcoreboot-c5651568ea63aedc92669c5447c0c9755e726244.tar.xz
mb/google/hatch: Enable/disable GPIO clock gating
Before the system enters S0ix or S3, each GPIO community will have its dynamic clock gating turned on. Upon return to S0, the dynamic clock gating will be turned back off. BUG=b:130764684 BRANCH=none TEST=Used dut-power to verify that the clock gating is enabled in S0ix and S3. Also used Store(..., Debug) statements in the ASL code to verify it was getting called. Change-Id: I20ff2aac035eaa5912af6c946d837567a4918bbf Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34180 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/mainboard')
-rw-r--r--src/mainboard/google/hatch/dsdt.asl3
-rw-r--r--src/mainboard/google/hatch/mainboard.asl57
2 files changed, 60 insertions, 0 deletions
diff --git a/src/mainboard/google/hatch/dsdt.asl b/src/mainboard/google/hatch/dsdt.asl
index 87e98ea925..e2959a788a 100644
--- a/src/mainboard/google/hatch/dsdt.asl
+++ b/src/mainboard/google/hatch/dsdt.asl
@@ -41,6 +41,9 @@ DefinitionBlock(
#include <soc/intel/cannonlake/acpi/northbridge.asl>
#include <soc/intel/cannonlake/acpi/southbridge.asl>
}
+
+ /* Mainboard hooks */
+ #include "mainboard.asl"
}
#if CONFIG(CHROMEOS)
diff --git a/src/mainboard/google/hatch/mainboard.asl b/src/mainboard/google/hatch/mainboard.asl
new file mode 100644
index 0000000000..dff1a75959
--- /dev/null
+++ b/src/mainboard/google/hatch/mainboard.asl
@@ -0,0 +1,57 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2019 Google, LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <intelblocks/gpio.h>
+
+Method (LOCL, 1, Serialized)
+{
+ For (Local0 = 0, Local0 < 5, Local0++)
+ {
+ \_SB.PCI0.CGPM (Local0, Arg0)
+ }
+}
+
+/*
+ * Method called from _PTS prior to system sleep state entry
+ * Enables dynamic clock gating for all 5 GPIO communities
+ */
+Method (MPTS, 1, Serialized)
+{
+ LOCL (MISCCFG_ENABLE_GPIO_PM_CONFIG)
+}
+
+/*
+ * Method called from _WAK prior to system sleep state wakeup
+ * Disables dynamic clock gating for all 5 GPIO communities
+ */
+Method (MWAK, 1, Serialized)
+{
+ LOCL (0)
+}
+
+/*
+ * S0ix Entry/Exit Notifications
+ * Called from \_SB.LPID._DSM
+ */
+Method (MS0X, 1, Serialized)
+{
+ If (Arg0 == 1) {
+ /* S0ix Entry */
+ LOCL (MISCCFG_ENABLE_GPIO_PM_CONFIG)
+ } Else {
+ /* S0ix Exit */
+ LOCL (0)
+ }
+}